BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20130310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20131103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20140309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20141102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20150308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20151101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20160313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20161106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20190310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20191103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180607T150000
DTEND;TZID=America/Los_Angeles:20180607T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14530-1528383600-1528387200@www.cecs.uci.edu
SUMMARY:Modeling and Co-Design of Multi-domain Cyber-Physical Systems
DESCRIPTION:Name: Jiang Wan \nDate: Friday\, June 1 \nTime: 3:00 — 5:00 PM \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Mohammad Al Faruque\, Rainer Doemer \nAbstract: \nCyber-Physical Systems (CPS) are integration of computation and physical processes connected through networks. The high complexity of cross-domain engineering in combination with the pressure for system innovation\, higher quality\, time-to-market\, and budget constraints make it imperative for engineers to use integrated engineering methods and tools for CPS design. However\, existing computer-based engineering tools are mainly focused on a particular domain and therefore it is challenging to perform system-level analysis for CPS due to the difficulty of knowledge integration from different domains. This thesis studies the problem in the modeling of cross-domain CPS. Problems in the modeling of both functional and non-functional requirements during CPS design are explored and a functional model-based approach is proposed for high level CPS modeling. Moreover\, targeting the security requirement in CPS\, which is one of the key non-functional requirements in CPS\, physics-based models and solutions are proposed in this thesis. \n 
URL:https://www.cecs.uci.edu/event/modeling-and-co-design-of-multi-domain-cyber-physical-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180606T150000
DTEND;TZID=America/Los_Angeles:20180606T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14529-1528297200-1528300800@www.cecs.uci.edu
SUMMARY:Reliable and Energy Efficient Battery-Powered Cyber-Physical Systems
DESCRIPTION:Name: Korosh Vatanparvar\nDate: Wednesday\, May 30th \nTime: 3:00 — 5:00 PM \nLocation: Calit2 3008 \nCommittee: Professor Prof. Mohammad Al Faruque (Chair) \nAbstract: \nCyber-Physical Systems (CPS) were presented as a solution to multidisciplinary integration and control in embedded systems. They provide seamless interactions between cyber and physical domains\, enabling more intelligent and complicated control applications. However\, CPS face the challenges of reliability and energy efficiency since they mainly rely on batteries for power supply. \nWe investigate these issues with Electric Vehicles (EV) which are common battery-powered CPS. EV were introduced as a mean of transportation to address environmental problems like air and noise pollution. However\, their stringent design constraints\, especially on battery packs\, create challenges of limited driving range and battery lifetime for daily drivers and manufacturers. Design automation community has been addressing these by developing more efficient and dependable devices and control methodologies. Our contributions in this thesis will embrace: \n1) novel machine learning and physics-based modeling techniques to capture CPS dynamics more accurately; 2) unique optimization problem formulations to make optimal control decisions; and 3)intelligent control methodologies that leverage the modeling and interaction within CPS to achieve reliable and efficient operation. These contributions are applied to the systems in EV such as navigation system\, climate control\, and battery management system. Our objectives are to further extend the EV driving range and prolong the battery lifetime while maintaining similar driving experience and comfort for passengers. \n 
URL:https://www.cecs.uci.edu/event/reliable-and-energy-efficient-battery-powered-cyber-physical-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180517T150000
DTEND;TZID=America/Los_Angeles:20180517T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14526-1526569200-1526572800@www.cecs.uci.edu
SUMMARY:Reflective On-Chip Resource Management Policies for Energy-Efficient Heterogeneous Multiprocessors
DESCRIPTION:Name: Tiago Mück\nDate: May 16\, 2018 \nTime: 2:00pm \nLocation: Donald Bren Hall 2011 \nCommittee: Nikil Dutt (Chair)\, Alex Nicolau\, Tony Givargis \nAbstract: \nEffective exploitation of power-performance tradeoffs in heterogeneous many-core platforms (HMPs)\, requires intelligent on-chip resource management at different layers\, in particular at the operating system level. Operating systems need to continuously analyze the application behavior and find a proper answer for questions such as: What is the most power efficient core type to execute the application without violating its performance requirements? or Which option is more power-efficient for the current application: an out-of-order core at a lower frequency or an inorder core at a higher frequency?\nUnfortunately\, existing operating systems (e.g. Linux) do not offer mechanisms to properly address these questions and therefore are unable to fully exploit architectural heterogeneity for scalable energy-efficient execution of dynamic workloads.\nThis dissertation proposes a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software.\n\nThe general idea of reflection is to change your actions based on both external feedback and introspection (i.e.\, self-assessment).\n\n\nFrom a practical computer system perspective\, reflection means performing resource management actions considering both sensing information (e.g.\, readings from performance counters\, power sensors\, etc.) to assess the current system state\, as well as models to predict the behavior of the system before performing an action.\nIn this context\, this dissertation describes MARS\, a Middleware for Adaptive Reflective computer Systems. MARS consists of a framework and a set of models for creating reflective resource managers. MARS is implemented and evaluated on top a real Linux-based platform. Furthermore\, MARS also provides an offline simulation infrastructure for fast prototyping of policies and large-scale or long-term policy evaluation.\n\nExperimental evaluation shows that MARS’s models allow different policies for task mapping and dynamic voltage scaling to be seamlessly integrated\, resulting in up-to 1.8x energy efficiency improvements without performance degradation when compared to vanilla Linux.
URL:https://www.cecs.uci.edu/event/reflective-on-chip-resource-management-policies-for-energy-efficient-heterogeneous-multiprocessors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14525-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:SIMD Assisted Fault Detection and Fault Attack Mitigation
DESCRIPTION:Name: Zhi Chen\nDate: May 15\, 2018 \nTime: 2:30pm \nLocation: Donald Bren Hall 3011 \nCommittee: Professor Alex Nicolau (Chair)\, Alex Veidenbaum\, Nikil Dutt \nAbstract: \nModern processors continue to aggressively scale down the feature size and reduce voltage levels to run faster and be more energy efficient. However\, this trend also poses significant reliability concern as it makes transistors more susceptible to soft errors. Soft errors are transient. Although they don’t impair the computing systems permanently\, these errors can corrupt the output of a program or even crash the entire system. Hardware or software redundant techniques could be used to detect errors during the execution of a program. However\, hardware redundancy\, e.g. DMR (dual-modular redundancy) and TMR (triple-modular redundancy)\, leads to significant area overhead and very high energy cost. Software redundancy\, e.g. instruction duplication\, has lower performance and energy penalty and  virtually no hardware cost by sacrificing a small degree of error coverage. Yet commodity processors generally don’t require “five-nines” reliability as they are not mission-critical. Instead\, performance and energy consumption have more priority. This dissertation proposes a novel approach to instruction duplication\, which exploits the redundancy within SIMD instructions. The key idea is to pack the original data and its duplicate in the different lanes of the same vector register instead of executing two scalar instructions separately as these registers are underutilized on most applications. The proposed solution is implemented in the LLVM compiler as a stand-alone pass. Evaluation on a host of benchmarks reveal that proposed SIMD-based error detection technique causes much less performance\, code size\, and energy overheads.\n\nThis dissertation further extends the proposed approach as a countermeasure to protect cryptographic algorithms. These algorithms are widely adopted in modern processors and embedded systems to protect information. A number of popular cryptographic algorithms in the Libgcrypt library are protected using the SIMD-based instruction duplication technique. A large amount of errors are injected to these algorithms. The results show that almost all injected faults can be detected with reasonable performance and code size cost.\n 
URL:https://www.cecs.uci.edu/event/simd-assisted-fault-detection-and-fault-attack-mitigation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180503T150000
DTEND;TZID=America/Los_Angeles:20180503T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14517-1525359600-1525363200@www.cecs.uci.edu
SUMMARY:"Efficient Acceleration of Computation Using Associative In-memory Processing"
DESCRIPTION:Title: “Efficient Acceleration of Computation Using Associative In-memory Processing”\nSpeaker: Hasan Erdem Yantir\, University of California\, Irvine \nDate and Time: Monday\, May 14\, 2018 at 9:00AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi (Chair)\, Ahmed Eltawil\, Rainer Doemer \nAbstract: \nThe complexity of the computational problems is rising faster than the computational platforms’ capabilities. This forces researchers to find alternative paradigms and methods for efficient computing. One promising paradigm is accelerating compute-intensive kernels using in-memory computing accelerators since memory is the major bottleneck that limits the amount of parallelism and performance of a system and dominates energy consumption in computation. Leveraging the memory intensive nature of big data applications\, an in-memory-based computation system can be presented where logic can be replaced by memory structures\, virtually eliminating the need for memory load/store operations during computation. The massive parallelism enabled by such a paradigm results in highly scalable structures. \nThe present thesis is studied against this background. The objective is to conduct a broad perspective research on in-memory computing. For this purpose\, associative computing architectures (i.e.\, Associative Processors\, or AP) are built by both traditional (SRAM) and emerging (ReRAM) memory technologies together with their corresponding software frameworks. For ReRAM-based APs\, the reliability concerns coming with the emerging memories are resolved. Architectural innovations are developed to increase the energy efficiency. Furthermore\, approximate computing approach is introduced for APs to perform efficient/low-power approximate in-memory computing for the tasks which can tolerate some accuracy lost.  The works also propose a novel two-dimensional in-memory computing architecture to cope with the existing deficiencies of the traditional one-dimensional AP architectures.
URL:https://www.cecs.uci.edu/event/efficient-acceleration-of-computation-using-associative-in-memory-processing/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180411T150000
DTEND;TZID=America/Los_Angeles:20180411T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190729Z
UID:14516-1523458800-1523462400@www.cecs.uci.edu
SUMMARY:"A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models"
DESCRIPTION:Title: “A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models”\nSpeaker: Tim Schmidt\, University of California\, Irvine \nDate and Time: Friday\, April 20\, 2018 at 10:00AM-11:00PM \nLocation: Engineering Hall 3206 \nCommittee: Professor Rainer Doemer (Chair)\, Fadi Kurdahi\, Kwei-Jay Lin \nAbstract: \nThe design of embedded systems is a well-established research domain for many decades. However\, the constantly increasing complexity and requirements of state-of-the-art embed- ded systems pushes designers to new challenges while maintaining established design methodologies. Embedded system design uses the concept of Discrete Event Simulation (DES) to prototype and test the interaction of individual components. \nIn this dissertation\, we provide the Recoding Infrastructure for SystemC (RISC) compiler framework to perform static and hybrid analysis of IEEE SystemC models. On one hand\, RISC generates thread communication charts to visualize the communication between individual design components. The\nvisualization respects the underlying discrete event simulation semantics and illustrates the individual synchronization steps. On the other hand\, RISC translates a sequential model into a parallel model\nwhich effectively utilizes multi- and many-core host simulation platforms for faster simulation. This work extends the conflict analysis capabilities for libraries\, dynamic memory allocation\, channel instance awareness\, and references. Additionally\, the traditional thread level parallelism is extended with data level parallelism for even faster simulation.
URL:https://www.cecs.uci.edu/event/a-compiler-infrastructure-for-static-and-hybrid-analysis-of-discrete-event-system-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171114T150000
DTEND;TZID=America/Los_Angeles:20171114T160000
DTSTAMP:20231011T190709Z
CREATED:20231011T190702Z
LAST-MODIFIED:20231011T190709Z
UID:14501-1510671600-1510675200@www.cecs.uci.edu
SUMMARY:"Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems"
DESCRIPTION:Title: “Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems”\nSpeaker: Majid Namaki Shoushtari\, University of California\, Irvine \nDate and Time: Tuesday\, November 7\, 2017 at 11:00AM-12:00PM \nLocation: Donald Bren Hall 2011 \nAbstract:\nThe growing computing demands of emerging application domains such as Recognition/Mining/Synthesis (RMS)\, visual computing\, wearable devices and the Internet of Things (IoT) has driven the move towards manycore architectures to better manage tradeoffs among performance\, energy efficiency\, and reliability.\nThe memory hierarchy of manycore architectures has a major impact on their overall performance\, energy efficiency and reliability. We identify three major problems that make traditional memory hierarchies unattractive for manycore architectures and their data-intensive workloads: (1) they are power hungry and not a good fit for manycores in face of dark silicon\, (2) they are not adaptable to the variable workload’s requirements and memory behavior\, and (3) they are not scalable due to coherence overheads. \nThis thesis argues that many of these inefficiencies are the result of software-agnostic hardware-managed memory hierarchies. Application semantics and behavior captured in software can be exploited to more efficiently manage the memory hierarchy. This thesis exploits some of this information and proposes a number of techniques to mitigate the aforementioned inefficiencies in two broad contexts: (1) explicit management of hybrid cache-SPM memory hierarchy\, and (2) exploiting approximate computing to improve the energy efficiency of the memory hierarchy.\nWe first present the required hardware and software support for a software-assisted memory hierarchy that is composed of distributed memories which can be partitioned between caches and SPMs at runtime. We discuss our SPM APIs\, the protocol needed for data movements\, and our approach for explicit management of shared data.\nNext\, we augment caches and SPMs in this hierarchy with approximation support in order to improve the energy efficiency of the memory subsystem when running approximate programs.\nFinally\, we discuss a quality-configurable memory approximation strategy using formal control theory that adjusts the level of approximation at runtime depending on the desired quality for the program’s output. \n 
URL:https://www.cecs.uci.edu/event/software-assists-to-on-chip-memory-hierarchy-of-manycore-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170531T150000
DTEND;TZID=America/Los_Angeles:20170531T160000
DTSTAMP:20231011T190636Z
CREATED:20231011T190636Z
LAST-MODIFIED:20231011T190636Z
UID:14486-1496242800-1496246400@www.cecs.uci.edu
SUMMARY:Quoc-Viet Dang PhD Defense
DESCRIPTION:Name: Quoc-Viet Dang\nDate: May 30\, 2017 \nTime: 02:00 P.M \nLocation: Engineering Hall 3206 \nCommittee: Professor Daniel Gajski (Chair)\, Fadi Kurdahi\, Rainer Doemer \nAbstract: \nPublic education is on the brink of a potential crisis attempting to significantly increase student enrollment while maintaining quality of education. Online courses have been proposed and debated among members of the UC regents\, numerous college administrators\, faculty\, and students. On one hand\, online education can reduce overhead while enrolling more students. Directly translating the classroom lectures and materials to an online environment does not necessarily produce equivalent student performance and satisfaction from the course compared to an in-class environment. Since there is no universal standard for online education\, erratic and inconsistent results have been achieved in terms of student performance and costs to students as well as administration. A hybrid scalable teaching and learning methodology is required by both educators and students to achieve the greatest advantages of using today’s technology and apply it toward improving student performance and participation. \nThis dissertation presents a methodology and system to provide a more individualized and responsive learning environment for students in large hybrid and online university courses while keeping overall costs and time commitment down as well as improve overall student performance. The Universal Personal Advisor\, the implemented learning design tool of this research\, is developed based on multi-disciplinary metrics and studies from the fields of Psychology\, Education\, and Engineering. A primary limiting resource for both students and instructors is time. By automating some basic key interactions that may occur between students and instructors\, hours of each individual’s time can be saved\, maximizing the quality of the available in-person interactions to occur during a course while allowing for a more scalable sized classroom environment.
URL:https://www.cecs.uci.edu/event/quoc-viet-dang-phd-defense/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170526T150000
DTEND;TZID=America/Los_Angeles:20170526T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190642Z
UID:14485-1495810800-1495814400@www.cecs.uci.edu
SUMMARY:Robust Data Hiding in Multimedia for Authentication and Ownership Protection
DESCRIPTION:Name: Farhan A. Alenizi\nDate: May 26th\, 2017 \nTime: 10:00 AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi \nAbstract: \nEstablishing robust and blind data hiding techniques in multimedia is very important for authentication\, ownership protection and security. The multimedia being used may include images\, videos and 3D mesh objects. A hybrid pyramid Discrete-Wavelet-Transform (DWT) Singular-Value-Decomposition (SVD) data hiding scheme for video authentication and ownership protection is proposed. The data being hidden will be in the shape of a main  color logo image watermark and another secondary Black and White (B&W) logo image.   The color watermark will be decomposed to Bit-Slices.   A pyramid transform is performed on the Y-frames of a video stream resulting in error images;  then\, a Discrete Wavelet Transform (DWT) process is implemented using orthonormal filter banks on these  error images\, and the Bit-Slices watermarks are inserted in one or more of the resulting subbands in a way that is fully controlled by the owner; then\, the watermarked video is reconstructed. SVD will be performed on the color watermark Bit-Slices. A secondary B&W watermark will be inserted in the main color watermark using another SVD process.     The reconstruction was perfect without attacks\, while the average Bit-Error-Rates (BER’s) achieved under attacks are in the limits of  2% for the color watermark and 5% for the secondary watermark; meanwhile\,  the mean Peak Signal-to-Noise Ratio (PSNR) is 57 dB. Furthermore\, a selective denoising filter to eliminate the noise in video frames is proposed; and the performance with data hiding is evaluated. \n  \nMoreover\, a 3D mesh blind  optimized watermarking   technique is proposed in this research. The technique relies on  the displacement process of  the vertices locations depending on the modification of the  variances of the vertices’s norms. Statistical analysis were performed to establish the proper distributions that best fit each mesh\, and hence establishing the bins sizes.   Experimental results showed that the approach is robust in terms of both the perceptual  and the quantitative  qualities. \n  \nIn conclusion\,  the degree of robustness and security  of the  proposed techniques are shown. Also the schemes that can be adopted to further enhance the performance\,  and the future work that can be done in the field are introduced. \n 
URL:https://www.cecs.uci.edu/event/robust-data-hiding-in-multimedia-for-authentication-and-ownership-protection/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170515T150000
DTEND;TZID=America/Los_Angeles:20170515T160000
DTSTAMP:20231011T190638Z
CREATED:20231011T190638Z
LAST-MODIFIED:20231011T190638Z
UID:14490-1494860400-1494864000@www.cecs.uci.edu
SUMMARY:Millimeter-wave and Sub-THz Signal Generation and Detection in Silicon Technologies
DESCRIPTION:Name: Peyman Nazari\nDate: May 15\, 2017 \nTime: 10:00 AM \nCommittee: Prof. Payam Heydari (Chair). Prof. Michael Green\, Prof. Ahmed Eltawil \nAbstract:  \nMM-wave/sub-Terahertz (THz) signal generation\, radiation\, and detection have become increasingly attractive due to its fast-growing applications in spectroscopy\, radar\, biomedical and security imaging as well as high-speed wireless communication.\n\n\nSilicon technology\, in one hand\, offering high-density signal processing capabilities due to aggressive scaling of its feature size\, and on the other hand\, allowing integration of mm-wave/THz antenna elements owing to their shrunk footprint at these bands\, is well-suited for implementation of fully-integrated multi-antenna mm-wave/THz wireless System-on-Chips (SoC’s).\n\n\nPerformance of such system is dominantly governed by the quality and efficiency of signal generation\, transmission\, and detection. Passive and active components as means of realizing these functionalities must be optimized for operation at these frequency ranges. However\, excessive loss of on-chip passive components and limited gain and output power of transistors at such high frequencies demand novel passive and active structures. Furthermore\, high level of integration implies that the co-design of front-end components leads to a better end-to-end performance\, thus a holistic design methodology must be employed. Radiation characteristics of the wireless signal must also be engineered to improve its transmission quality. For example\, circularly polarized radiation is found to be a viable choice for many imaging and communication applications by exhibiting excellent robustness against de-polarization effects.\n\n\nIn this dissertation\, silicon realization of on-chip waveguides\, as low loss mediums for high-frequency wave propagation\, is explored and implementations of low-loss cavity-backed passives are discussed. Furthermore\, a silicon-integrated IMPATT diode\, together with its fabrication and modeling is introduced as a solution for obtaining active behavior beyond fmax of transistors. Next\, a high-power/efficiency mm-wave circularly-polarized cavity-backed radiator\, employing a multi-port multi-function passive network as a resonator\, power combiner\, and antenna\, is introduced. Necessary conditions for robust operation of such multi-port oscillators/radiators are also derived. Fabricated in a 0.13µm SiGe BiCMOS process\, the prototype chip achieves 14.2dBm EIRP\, -99.3dBc/Hz phase noise at 1MHz offset\, and 5.2% DC-to-EIRP conversion efficiency which is the highest reported value among silicon-based radiators not using silicon lens or substrate processing.\n\n\nFinally\, a 210GHz low noise amplifier (LNA) is presented to address the detection challenges. This LNA\, achieves 18dB of gain\, with less than 12dB noise-figure and 3dB bandwidth of more than 15GHz\, thereby showing best performance metrics among prior work. This is achieved by incorporating circuit and EM techniques enabling simultaneous optimization of stable gain-\, noise- and bandwidth-performance parameters at this frequency range.
URL:https://www.cecs.uci.edu/event/millimeter-wave-and-sub-thz-signal-generation-and-detection-in-silicon-technologies/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170307T150000
DTEND;TZID=America/Los_Angeles:20170307T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14482-1488898800-1488902400@www.cecs.uci.edu
SUMMARY:Optimizing Many-Threads-to-Many-Cores Mapping in Parallel Electronic System Level Simulation
DESCRIPTION:Name: Guantao Liu\nDate: March 2\, 2017 \nTime: 4:00 PM \nLocation: Engineering Hall 3206 \nCommittee: Rainer Doemer (Chair)\, Kwei-Jay Lin\, Mohammad Al Faruque \nAbstract: \nIn hardware/software co-design\, Discrete Event Simulation (DES) has been in use for decades to verify and validate the functionality of Electronic System Level (ESL) models. Since the parallel computing platforms are readily available today\, many Parallel Discrete Event Simulation (PDES) approaches are proposed to improve the simulation performance. However\, as the thread parallelism increases in ESL designs and core count multiplies on multi-core and many-core platforms\, thread-to-core mapping becomes critical in PDES. \nIn this dissertation\, we propose a computation- and communication-aware approach to optimize thread mapping for parallel ESL simulation\, with the aims of load balancing and communication minimization. As we identify that the order of dispatching parallel threads has a significant influence on the total simulation time\, and Longest Job First (LJF) shows better performance than the Linux default thread dispatch policy\, we first propose a segment- aware LJF scheduler for PDES. Our segment-aware scheduler can accurately predict the run time of the thread segments ahead\, and thus make better dispatching decisions. Next\, we define the concept of core distance for multi-core and many-core architectures\, which quantifies core-to-core communication latency and characterizes processor hierarchies. For many-core architectures using directory-based cache coherence protocols\, we observe that core-to-core transfers are not always significantly faster than main memory accesses\, and the core-to-core communication latency depends not only on the physical placement on the chip\, but also on the location of the distributed cache tag directory. Thus\, using a memory ping-pong benchmark\, we quantify the core distance on a ring-network many-core platform and propose an algorithm to optimize thread-to-core mapping in order to minimize on-chip communication overhead. Altogether\, based on a static analysis of communication patterns and core distance and a dynamic profiling of computation load\, our proposed framework utilizes a heuristic graph partitioning algorithm and automatically generates an optimized thread mapping\, which minimizes inter-chip communication overhead. In our systematic evaluation\, our approach consistently shows a significant performance gain on top of the order-of-magnitude speedup of PDES. \nThe contributions of this dissertation include a segment-aware multi-core scheduler\, core distance profiling\, a communication-aware thread mapping framework\, together with an open-source software package for Out-of-Order PDES.
URL:https://www.cecs.uci.edu/event/optimizing-many-threads-to-many-cores-mapping-in-parallel-electronic-system-level-simulation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170221T150000
DTEND;TZID=America/Los_Angeles:20170221T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14481-1487689200-1487692800@www.cecs.uci.edu
SUMMARY:Low Power Reliable Design using Pulsed Latch Circuits
DESCRIPTION:Name: Wael Mahmoud Elsharkasy \nDate: February 15\, 2017 \nTime: 11:00 AM \nLocation: Engineering Hall 3206 \nCommittee: Prof. Fadi J. Kurdahi\, Prof. Ahmed Eltawil\, Rainer Doemer \nAbstract: \nSystem-on-Chip (SoC) faced lots of challenges over the past decade. With nowadays applications centered around Internet-of-Everything (IoE)\, these challenges are expected to be more critical. Among these challenges are the reduction of power consumption for better energy efficiency\, the overcoming of different sources of variations to ensure reliable operation and the reduction of design area to reduce the cost and increase the integration. As a result\, chip designers find themselves facing lots of problems\, trying to build reliable systems that integrate complex level of functionality\, on a minimum die size and with a limited power budgets. Among different circuit components in every chip\, memory components are of great concern. They consume the majority of the chip area and power\, in addition to affecting the entire chip performance and reliability. These include large memory arrays\, caches\, register files and different sequential elements in the logic paths. Sequential elements play an important and critical role in modern synchronous CMOS circuits. Indeed\, they can represent up to 50% of the standard cells used in a chip. In addition\, the power consumption of the clock tree\, including these elements can be more than half of the total chip power. In addition\, they come in the second place after memory to be affected by different sources of variation. Hence\, efficient implementation of these elements is of great importance for the design of energy efficient and reliable integrated circuits. Pulsed latches have been proposed as efficient replacement of flip-flops in the implementation of sequential element. They can achieve higher performance when compared to traditional flip-flop\, and can be designed to be smaller in area and more power efficient. However\, the operation of pulsed latch is more sensitive to process\, voltage and temperature (PVT) variations. In this thesis\, we are proposing a methodology to study the reliability of pulsed latches and we have used it to evaluate the effect of PVT variations on their behavior. In addition\, novel approaches to enhance the reliability of pulsed latches without significant degradation in performance\, area or power are presented. Also\, since sequential elements can be used to build small size register files\, pulsed latch implementation of register files are discussed and compared to other traditional implementations\, including SRAM and flip-flops. In addition\, since multiport register files are very beneficial for quite few applications\, novel implementations of multiport register files are also presented. The proposed implementation is proved to highly reduce the significant overhead in area\, power and latency associated with the traditional way of designing multiport register files.
URL:https://www.cecs.uci.edu/event/low-power-reliable-design-using-pulsed-latch-circuits/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170131T150000
DTEND;TZID=America/Los_Angeles:20170131T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14479-1485874800-1485878400@www.cecs.uci.edu
SUMMARY:Runtime Memory Management in Many-core Systems
DESCRIPTION:Name: Hossein Tajik\nDate: November 15\, 2016 \nTime: 3:00PM – 4:00PM \nLocation: DBH 3011 Conference Room \nCommittee: Nikil Dutt (Chair)\, Tony Givargis\, Alex Nicolau \nAbstract: \nWith the increasing number of cores on a chip\, we are moving towards an era where many-core platforms will soon be ubiquitous. Efficient use of tens to hundreds of cores on a chip and their memory resources comes with unique challenges. \nIn this dissertation\, we propose SPMPool: a scalable platform for sharing Software Programmable Memories (SPMs). The SPMPool approach exploits underutilized memory resources by dynamically sharing SPM resources between applications running on different cores and adapts to the overall memory requirements of multiple applications that are concurrently executing on the many-core platform. We propose both central and distributed management schemes for SPMPool and study the efficiency of auction-based mechanisms in solving the memory mapping problem. We also propose offline and online memory phase detection methods in order to increase the adaptivity of memory management to temporal changes in memory requirements of a single application. The runtime memory management schemes proposed in this dissertation enable better performance and power for many-core systems.
URL:https://www.cecs.uci.edu/event/runtime-memory-management-in-many-core-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170130T150000
DTEND;TZID=America/Los_Angeles:20170130T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14492-1485788400-1485792000@www.cecs.uci.edu
SUMMARY:On Optimizing the Performance of Interference-Limited Wireless Systems
DESCRIPTION:Name: Rana A. Abdelaal\nDate: January 30\, 2017 \nTime: 1:00 PM \nLocation: Engineering Hall 3106 \nCommittee: Professor Ahmed Eltawil \nAbstract: \nMulti Input Multi Output (MIMO) technology has seen prolific use to achieve higher data rates and an improved communication experience for cellular systems. However\, one of the challenging problems in MIMO systems is interference. Interference limits the system performance in terms of rate and reliability. In this thesis\, we analyze methods that provide high performance over interference-limited wireless networks such as Long Term Evolution (LTE) and WiFi. In this thesis\, we tackle different sources of interference. One of the interference sources is the neighboring interference\, we propose methods that include an optimized solution that models the interference as correlated noise\, and uses its statistical information to jointly optimize the base station precoding and user receiver design of LTE systems. We study the benefits of exploiting interference in terms of both probability of error and signal-to-noise ratio (SNR). In addition\, we compare the proposed method with the conventional beamforming and maximum ratio combining (MRC). One of the key challenges to enable high data rates in the downlink of LTE is the precoding and receiver design. We focus primarily on the UE and the base station (BS) processing\, particularly on estimating and using the interference resulting from neighboring stations. In this thesis\, we propose a receiver design that performs well in the presence of interference. Furthermore\, we present a precoding scheme that the BS can use to maximize the signal-to-interference plus noise-ratio (SINR). An interference free scenario is used as a benchmark to evaluate the proposed system performance. In this thesis\, we optimize the performance of LTE by tackling practical considerations that affects the system performance. We present a suboptimal practical way of estimating the interference and utilizing this information on the processing techniques used at both the UE and the eNodeB sides. We focus on managing both MU-MIMO interference and other cell interference. The proposed study improves system performance even under non-perfect channel knowledge\, enabling the throughput gains promised by MU-MIMO. \nOther types of interference exist in In-band full-duplex (IBFD) communication systems. IBFD is very promising in enhancing wireless LANs\, where full-duplex access points (APs) can support simultaneous uplink (UL) and downlink (DL) flows over the same frequency channel. One of the key challenges limiting IBFD benefits is interference. In this thesis\, we also propose a scheduling technique to manage interference in wireless LANs with full-duplex capability. We focus primarily on scheduling UL and DL stations (STAs) that can be efficiently served simultaneously. \nIt is very important to apply system knowledge to reduce power and/or improve performance. Thus\, we also aim at exploring energy and power management techniques for practical wireless communication systems. An important topic for practical communication systems is handling the interference due to the power amplifier nonlinearities. Managing this type of interference is of very high importance\, especially in Orthogonal Frequency-Division Multiple Access (OFDMA) based communication systems. Although\, OFDMA is the modulation of choice due to its robustness to time-dispersive radio channels\, low-complexity receivers\, and simple combining of \nsignals from multiple transmitters in broadcast networks. The transmitter design for OFDMA is more costly\, as the Peak-to-Average Power Ratio (PAPR) of an OFDMA signal is relatively high\, resulting in the need for highly linear RF power amplifiers (PA). This problem becomes more compounded when a large number of PAs is required\, as in Massive MIMO for example. In this thesis\, we discuss the impact of PAs on cellular systems. We show the constraints that PAs introduce\, and we take these constraints into consideration while searching for the optimum set of transmitter and receiver filters. Moreover\, we highlight how Massive MIMO cellular networks can relax PAs constraints resulting in low cost PAs\, while maintaining high performance. The performance is evaluated by showing the probability of error curves and signal-to-noise-ratio curves for different transmit powers and different number of transmit antennas. Another promising topic for efficient practical communication systems is Associative processors (APs). AP is a good candidate for in-memory computation\, however it has been deemed too costly and energy hungry in the past. The advent of ultra-dense resistive memories is changing this paradigm\, allowing for efficient in-memory associative processors. However\, with high levels of integration\, issues related to power density become the bottleneck. In this thesis\, we show the potential use of the approximate computing in wireless communication systems\, specifically\, we present Fast Fourier Transform (FFT) implemented by associative processor. Results confirm that approximate computing for in-memory associative processors is a viable approach to reduce power consumption while maintaining good performance. A promising approach to save energy is through reducing the bit width\, however reducing the bit width introduces errors that may affect the performance. In this thesis\, our goal is to adjust the bit width based on the channel SNR\, aiming at achieving good performance at reduced energy consumption. The mathematical approach that analytically describes the system performance under the reduced bit width noise is presented. Based on this model\, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves performance goals at reduced energy consumption. Simulation results show that the proposed algorithms can achieve up to 45% energy savings as compared to wireless communication systems with conventional FFT. \n 
URL:https://www.cecs.uci.edu/event/on-optimizing-the-performance-of-interference-limited-wireless-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161206T150000
DTEND;TZID=America/Los_Angeles:20161206T160000
DTSTAMP:20231011T190622Z
CREATED:20231011T190622Z
LAST-MODIFIED:20231011T190622Z
UID:14476-1481036400-1481040000@www.cecs.uci.edu
SUMMARY:Scalable Runtime support for Edge-To-Cloud integration of Distributed Sensing Systems
DESCRIPTION:Name: Brett Chien\nDate: November 29\, 2016 \nTime: 10:00AM \nLocation: EH 2210 \nCommittee: Pai H. Chou (Chair) \nAbstract:  \nWhile Internet-Of-Things (IoT) has drawn more attention to researchers and the public\, to build a complete system from the edge sensing units to the cloud services requires massive amount of efforts. Researchers with strong interests in collected information are often lost in various technologies\, including distributed sensing embedded systems\, bridge devices between Internet and local network\, and data backend services. \nThis work takes a cross-system\, script-based\, and semantic-enhanced approach to address the problem of lacking suitable runtime supports. We proposed a threaded code runtime support for edge sensing systems\, a script based wrapper on Physical-to-Cyber bridges\, and scalable middleware into the backend services. \nWith proposed runtime supports\, we are able to apply distributed sensing systems into real world applications quickly and explorer insights from collected information. As a result\, a building structure monitoring system is installed and allow civil researchers to develop algorithms to prevent disaster events. Body area sensing systems such as ECG monitoring\, CO2 detection\, and body movement are developed. This enables baby screening and detect potential heart problems. The results have shown that with proposed runtime supports applications can be realized quickly and scalable.
URL:https://www.cecs.uci.edu/event/scalable-runtime-support-for-edge-to-cloud-integration-of-distributed-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161114T150000
DTEND;TZID=America/Los_Angeles:20161114T160000
DTSTAMP:20231011T190617Z
CREATED:20231011T190617Z
LAST-MODIFIED:20231011T190617Z
UID:14475-1479135600-1479139200@www.cecs.uci.edu
SUMMARY:Resource Aggregation for Collaborative Projected Video from Multiple Mobile Devices
DESCRIPTION:Name: Hung Nguyen\nDate: November 17\, 2016 \nTime: 1:30 P.M. \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Aditi Majumder (Co-Chair) \nAbstract:  \nWe explore and develop an embedded real time system and associated algorithms that enable an aggregation of limited resource\, low-quality\, projection-enabled mobile devices to collaboratively produce a higher quality video stream for a superior viewing experience. Such a resource aggregation across multiple projector enabled devices can lead to a per unit resource savings while moving the cost to the aggregate. \nThe pico-projectors that are embedded in mobile devices such as cell phones have a much lower resolution and brightness than standard projectors. Tiling (putting the projection area of multiple projectors in a rectangular array overlapping them slightly around the boundary) and superimposing (putting the projection area of multiple projectors right on top of each other) multiples of such projectors\, registered via automated registration through the cameras residing within those mobile devices\, result in different ways of aggregating resources across these multiple devices. Evaluation of our proof-of-concept system shows significant improvement for each mobile device in two primary factors of bandwidth usage and power consumption when using a collaborative federation of projection-embedded mobile devices. \nThe portable\, low-power\, light weight\, small size pico-projectors are key components of projection-enabled mobile devices for the future. Due to the reduction of weight and dimension and the portability nature of the projector-enabled mobile devices\, the calibrated integrated systems are prone to physical un-stabilizing of the projected image during the presentation. Thus the auto re-calibration and projected video stabilization features during the presentation time becomes essential requirements to enhance user experience. The design\, algorithm\, and implementation methods for these features will be presented in the second part of the dissertation.
URL:https://www.cecs.uci.edu/event/resource-aggregation-for-collaborative-projected-video-from-multiple-mobile-devices/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161004T150000
DTEND;TZID=America/Los_Angeles:20161004T160000
DTSTAMP:20231011T190615Z
CREATED:20231011T190615Z
LAST-MODIFIED:20231011T190615Z
UID:14469-1475593200-1475596800@www.cecs.uci.edu
SUMMARY:Specification and Runtime Verification of Distributed Multiprocessor Systems: Languages\, Tools and Architectures
DESCRIPTION:Name: Ahmed Nassar\nDate: September 2\, 2016 \nTime: 12:00 P.M. \nLocation: EH 3403 \nCommittee: Fadi Kurdahi (Chair)\, Rainer Doemer\, Ahmed Eltawil \nAbstract: Post-Deployment runtime verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification and testing methods. This thesis is an attempt to tackle three major barriers that need to be surmounted before RV technologies become in widespread use:\nBarrier-1: Lack of an expressive\, yet efficiently monitorable\, specification language. Distributed software behavior is projected onto an observation interface consisting of data-carrying (or parameterized) events\, such as Linux system calls including argument values\, and self-replicating deterministic finite automata (SR-DFAs) are introduced for RV purposes as well as anomaly-based intrusion detection in embedded and general-purpose software systems based on these parametric traces.\nBarrier-2: The substantial performance and power overhead of pure software RV frameworks. NUVA\, which stands for nonuniform verification architecture\, a distributed automata-based RV architecture for software specifications in the form of SR-DFAs. NUVA has been implemented over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor and can be deployed on the FPGA fabric that will reside on all next-generation processor chips. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes.\nBarrier-3: Formal specifications are hard to formulate and maintain for evolving complex embedded and general-purpose software systems. Therefore\, specification mining has long ago been envisioned to play a key role in software verification\, modification and documentation. However\, in order to scale beyond simple\, library/API-level properties having short temporal spans\, specification mining tools need to support more expressive specification languages that can capture complex\, application-level properties. This thesis introduces a bio-inspired complete specification mining methodology for SR-DFAs using an iterative and interactive mining tool\, called ParaMiner. ParaMiner relies on novel mining algorithms invoking multiple-sequence alignment (MSA) techniques to enable learning specifications from temporal slices of software behavior while overcoming the initial-state uncertainty problem.\nSR-DFAs and ParaMiner have been leveraged in a new specification-based intrusion detection (ID) framework that protects distributed\, reactive computing systems against cyberattacks having very sparse signatures\, arbitrarily long time spans and wide attack fronts. Such attacks lie outside the scope of conventional anomaly-based ID methods which typically work with short event windows and ignore manipulated data objects\, such as files and sockets. We demonstrate the effectiveness of the constructed SR-DFAs at classifying as well as resolving subtle behaviors typical of cyberattacks with varying evasion parameter values.
URL:https://www.cecs.uci.edu/event/specification-and-runtime-verification-of-distributed-multiprocessor-systems-languages-tools-and-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160818T150000
DTEND;TZID=America/Los_Angeles:20160818T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190553Z
LAST-MODIFIED:20231011T190555Z
UID:14449-1471532400-1471536000@www.cecs.uci.edu
SUMMARY:PhD Defense:
DESCRIPTION:Name:  Aras Pirbadian\nDate: August 29\, 2016 \nTime: 3:30pm \nLocation:  EH 3403 \nCommittee: Ahmed Eltawil (Chair)\, Fadi Kurdahi\, Rainer Doemer \nWith the continued scaling of chip manufacturing technologies\, the significance of process variation in performance of the systems is increasing. Specifically\, process variation results in growing voltage and frequency overhead margins required to ensure error free operation of circuits. However\, the traditional practice of overdesigning the systems to cover process variation is no longer an efficient design methodology in an age with high demands for processing power and limited energy supplies. In this dissertation\, a novel analytical model is proposed to predict the required margin accurately in the early stages of design space exploration. The model can be used to optimize the system overhead in error free calculations or to release the bound by full correctness in error tolerant parts of systems and optimize the energy vs. performance trade-off. Additionally\, this model also considers the statistics of the inputs of the circuit as compared to other existing efforts enabling it to achieve close predictions of full circuit simulation results in a short time. This model is finally used in an adaptive carry select/ripple carry adder configuration to demonstrate the potential achievable power savings. \nGrowing variation in newer technology nodes is not always a negative side effect. The increased inherent randomness in the process manufacturing technology can be utilized to develop unique physically unclonable functions (PUFs). These functions are irreproducible hardware-based authenticating systems\, which do not require memory-based storage. A low overhead delay-based PUF using the variation of the silicon manufacturing is also proposed in the second part of this work. The proposed PUF uses a simple and efficient structure to convert the randomness of the manufacturing process into random responses to fixed challenges in identically designed circuits.
URL:https://www.cecs.uci.edu/event/phd-defense/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160804T150000
DTEND;TZID=America/Los_Angeles:20160804T160000
DTSTAMP:20231011T190537Z
CREATED:20231011T190537Z
LAST-MODIFIED:20231011T190537Z
UID:14448-1470322800-1470326400@www.cecs.uci.edu
SUMMARY:Progression and Edge Intelligence Framework for IoT Systems
DESCRIPTION:Name:  Zhenqiu Huang\nDate: July 29\, 2016 \nTime: 10:00am \nLocation:  EH 4106 \nCommittee: Kwei-Jay Lin (Chair)\, Fadi Kurdahi\, Mohammad Al Faruque \nAbstract: This thesis studies the issues on building and managing future Internet of Things (IoT)\nsystems. IoT systems consist of distributed components with services for sensing\, processing\,\nand controlling through devices deployed in our living environment as part of the global\ncyber-physical ecosystem. \nSystems with perpetually running IoT devices may use a lot of energy. One challenge is to\nimplement good management policies for energy saving. In addition\, a large scale of devices\nmay be deployed in wide geographical areas through low bandwidth wireless communication\nnetworks. This brings the challenge of con
URL:https://www.cecs.uci.edu/event/progression-and-edge-intelligence-framework-for-iot-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14445-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Power Optimization for Medical Sensing Systems
DESCRIPTION:Name:  Jun Luan\nLocation:  EH 4106 \nDate: February 24\, 2016 \nTime: 1:00pm \nCommittee: Pai Chou (Chair)\, Mohammad Al Faruque\, Fadi Kurdahi \nAbstract:  \nMedical sensing systems collect and analyze the patients’ physiological data for monitoring\, aid or diagnostic purposes. System designers are faced with stringent requirements on not only correctness and safety but also power. Reference designs and multi-purpose platforms help to significantly shorten the development cycle. \nThis work takes a cross-layer\, system-level\, platform-based approach to addressing the problem of saving power in a class of portable medical system. We propose a low-power medical sensing system that can be used to monitor Electrocardiography (ECG)\, Photo- plethysmogram (PPG)\, and muscle tension. It also includes a hand gesture recognition system to aid mobility-impaired patients. \nWe explore the theory and application of a compressive sensing framework to medical signal processing. A novel compressive sensing-based ECG compression algorithm and a dominant frequency extraction-based PPG heart-rate calculation algorithm are proposed to reduce the system power. The unique combination of hardware structure and software signal-processing algorithms makes low-power design possible. The system test results show that the proposed system is superior to existing works in terms of power consumption and system size.
URL:https://www.cecs.uci.edu/event/power-optimization-for-medical-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14446-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Frameworks and Algorithms for Wearable Medical Applications
DESCRIPTION:Name:  SeungJae Lee\nDate:  April\, 5\, 2016 \nTime:  3:00p.m. \nLocation:  EH 4106 \nCommittee:  Pai H. Chou (Chair)\, Fadi Kurdahi\, Tony Givargis \nAbstract: \nWearable embedded systems with sensing\, communication\, and computing capabilities have given rise to innovations in e-health and telemedicine in general. The scope of such systems ranges from devices and mobile apps to cloud backend and analysis algorithms\, all of which must be well integrated. To manage the development\, operation\, and evolution of such complex systems\, a framework systematic framework is needed. This dissertation makes contributions in two parts. First is a framework for defining the structure of a wide range of wearable medical applications with modern cloud support. The second part includes several algorithms that can be plugged into this framework for making these systems more efficient in terms of processing performance and data size. We propose a novel QT analysis algorithm that can take advantage of GPU as well as in a server-client environment\, and we show competitive results in terms of both performance and energy consumption with or without parallelization. We also propose ECG compression techniques using trained overcomplete dictionary. After constructing the dictionary through learning process with a given dataset\, the signal can be compressed by sparse estimation using the trained dictionary. We propose reconstructing ECG signal from undersampled data based on compressive sensing framework that can reconstruct the ECG signals precisely from fewer samples so long as the signal is sparse or compressible. Together\, these algorithms operating in the context of our proposed framework validate the effectiveness of our structured approach to the framework for wearable medical application. \n 
URL:https://www.cecs.uci.edu/event/frameworks-and-algorithms-for-wearable-medical-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150729T150000
DTEND;TZID=America/Los_Angeles:20150729T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14444-1438182000-1438185600@www.cecs.uci.edu
SUMMARY:A Centralized IoT Middleware System for Devices Working Across Application Domains Using Self-descriptive Capability Profile
DESCRIPTION:Name: Chengjia Huo\nLocation: EH 4404 \nDate: September 30\, 2015 \nTime: 1pm \nCommittee: Pai H. Chou (chair)\, Phillip Sheu\, Rainer Doemer \nAbstract: \nThe Internet of Things (IoT) has been receiving growing attention in recent years as the next wave of computing revolution made possible by all types of networks of things (NoTs)\, where devices powered with low-cost\, miniature low-power systems-on-chip (SoC) with computing and communication capabilities\, and are bridged to the Internet with the assistance of gateways. More and more NoT device are designed to provide more than one functionalities to fulfill different requirements from the application domains. We believe that the true power of IoT is that functionalities of devices can work across application domains. In order to reveal the potential of IoT\, the description of a device’s capability needs to represent the functionalities that the device can provide. We discover the previous solutions on describing a device’s capability focus mainly on hiding the vendor-specific interfaces made by different manufacturers\, but they do not reflect different functionalities that a device provides. In this thesis\, the concept of device capability profile is proposed. Different from the previous solutions\, the device capability profile specified in the firmware of a device allows the device to work across different application domains. Together with device capability profile\, a centralized IoT middleware framework\, called rimware\, is proposed. Rimware tracks every device’s capability and state in a centralized manner and provides different ways for application domains to query against the device’s functionalities. In addition\, rimware utilizes the device capability profile to carry out the enforcement of the security and privacy throughout the communication with the devices. Moreover\, tasks can be scheduled through the rimware which enables functionalities from multiple devices to work together to fulfill the requirements from application domains. Optimization is applied on cases that one device working for multiple task simultaneously. An implementation of rimware that is specifically designed for BLE devices\, called BlueRim\, which takes advantages of BLE’s very long battery life on the device side and the cloud functionality on the centralized side is provided. The fundamental features of rimware have been validated in several real-world applications from different different domains while incurring minimal code size and communication overhead on BLE devices. We believe that our approach represents an important technology in taking IoT closer to realizing the full potentials.
URL:https://www.cecs.uci.edu/event/a-centralized-iot-middleware-system-for-devices-working-across-application-domains-using-self-descriptive-capability-profile/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150521T150000
DTEND;TZID=America/Los_Angeles:20150521T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14434-1432220400-1432224000@www.cecs.uci.edu
SUMMARY:CARL-SJR: A Socially Assistive Neurorobot for Autism Therapy and Research
DESCRIPTION:Name: Ting-Shuo Chou\nDate: May 21\, 2015 \nTime: 3:00pm – 5:00pm \nLocation: Social & Behavioral Sciences Gateway 2200 Conference Room \nCommittee Chair: Jeffrey Krichmar (Chair)\, Nikil Dutt\, Alexandru Nicolau \nAbstract: \nNeurodevelopmental disorders\, such as Attention-Deficit–Hyperactivity\nDisorder (ADHD) and Autism Spectrum Disorder (ASD)\, have core clinical\nsymptoms of inattention\, hyperactivity\, and impulsivity (often hyper-\nand hypo- responsiveness. These symptoms are often accompanied by\nreduced motor coordination and impaired sensory processing. We introduce\na Socially Assistive Robot (SAR) with the goal of automating therapy for\nchildren with neurodevelopmental disorders. The novel robot\, which is\ncalled Cognitive Anteater Robotics Laboratory – Spiking Judgment Robot\n(CARL-SJR)\, is designed for therapy and diagnosis. CARL-SJR is\nautonomous and capable of tactile sensing and interaction. A spiking\nneural network model and neurally inspired algorithms controls\nCARL-SJR’s behavior. By providing a large tactile sensing surface that\nencourages touching with hand movements\, CARL-SJR especially addresses\nimpairments in tactile sensitivity and social interaction observed in\nchildren with neurodevelopmental disorders. Using CARL-SJR\, we conducted\na pilot study where children with different neurodevelopment disorders\nshow different behavioral metrics and tactile movements. The results\nsuggest CARL-SJR might serve as a diagnose tool for developmental\ndisorders. Second\, we showed that the information carried by temporal\ncoding is higher than the traditional rate coding when decoding spike\ntrains in response to tactile movements. Third\, we implemented online\nlearning capabilities on CARL-SJR\, where the robot could associate a\nuser’s preferred color pattern displayed on the robot with the user’s\nhand sweep across the robot’s body. The emerged behaviors and neural\nactivities in the SNN are consistent with biological recordings. The\nunderlying neural mechanism in the SNN also serves as an alternative\nexplanation of how brains encode timing and associate (or learning) two\ntemporal separated events.
URL:https://www.cecs.uci.edu/event/carl-sjr-a-socially-assistive-neurorobot-for-autism-therapy-and-research/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150521T150000
DTEND;TZID=America/Los_Angeles:20150521T160000
DTSTAMP:20231011T190511Z
CREATED:20231011T190511Z
LAST-MODIFIED:20231011T190511Z
UID:14433-1432220400-1432224000@www.cecs.uci.edu
SUMMARY:Ensuring Reliability and Fault-Tolerance for the Cyber-Physical System Design
DESCRIPTION:Name: Volkan Gunes\nDate: May 27\, 2015 \nTime: 11:00AM – 12:00PM \nLocation: Donald Bren Hall 3013 Conference Room \nCommittee: Tony Givargis (Chair)\, Alexandru Nicolau\, Ian Harris\, Steffen Peter \nAbstract: \nThe cyber-physical system (CPS) is a term describing a broad range of\ncomplex\, multi-disciplinary\, physically-aware next generation engineered\nsystems that integrate embedded computing technologies (cyber part) into\nthe physical world. Sensors play an important role in this integration\nbecause they provide the data extracted from the physical world for the\ncyber systems to fulfill the decision making process. However\, this\nprocess is likely to be misled by incorrect data due to sensor fault\noccurrences. \nIn this dissertation\, the main focus is on sensor fault mitigation and\nachieving high reliability in CPS operations. One of the challenges we\nponder is timely event (e.g.\, motion as a phenomenon) detection in CPS\nunder possible faulty sensor conditions. In this regard\, our\ndemonstrative example of CPS is the falling ball example (FBE) using\nbinary event detectors (i.e.\, motion sensors)\, a controller\, and a\ncamera for timely motion detection of a falling ball. Another challenge\nwe ponder is satisfying thermal comfort and energy efficiency under\ncertain faulty sensor conditions in a multi-room building incorporating\ntemperature sensors\, controllers\, and heating\, ventilation\, and air\nconditioning (HVAC) systems as a CPS application. For both cases\, we\nadopt a model-based design (MBD) methodology to analyze the effect of\nsensor faults on the desired system outcome. We specify well-defined\nfault semantics for the event detectors and temperature sensors to make\nthe problem definition more clear. We provide a MATLAB/Simulink\nsimulation framework for our CPS examples. Besides having the\ntraditional CPS model that comprises the cyber\, interface (e.g. sensors\nand actuators) and physical models\, we develop fault models and a system\nevaluation model in Simulink and incorporate them into the CPS model. \nWe explore various techniques for fault mitigation in a holistic design\nperspective. Therefore\, the approaches presented in this study\ncontributes to the design of fault-tolerant CPSs. Furthermore\,\nconsidering compute demands of large scale CPSs\, we introduce the XGRID\nembedded many-core system-on-chip architecture. XGRID makes use of a\nnovel\, FPGA-like\, programmable interconnect infrastructure\, offering\nscalability and deterministic communication using hardware supported\nmessage passing among cores. We provide a conceptual mapping of control\nalgorithms for the automation of a multi-room building onto target XGRID\narchitecture. \nOur findings regarding reliable CPS design show that the physical system\nattributes (e.g.\, sensor placement and environmental effects) can be a\nmore dominant factor than the cyber system attributes on the system\noutcome. In addition\, sensor faults may lead to unsatisfactory system\noutcome in CPSs since CPSs heavily rely on sensor readings for decision\nmaking. Therefore\, the analysis of temporal and spatial correlations\nbetween sensor readings helps mitigate certain types of sensor faults\nand enable CPSs to utilize sensors’ data more efficiently for decision\nmaking.
URL:https://www.cecs.uci.edu/event/ensuring-reliability-and-fault-tolerance-for-the-cyber-physical-system-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150515T150000
DTEND;TZID=America/Los_Angeles:20150515T160000
DTSTAMP:20231011T190511Z
CREATED:20231011T190511Z
LAST-MODIFIED:20231011T190511Z
UID:14432-1431702000-1431705600@www.cecs.uci.edu
SUMMARY:Temperature-Aware Design for SoCs using Thermal Gradient Analysis
DESCRIPTION:Name: Jun Yong Shin\nDate: May 18th\, 2015 \nTime: 2:00PM \nLocation: EH2430\, Harut colloquia room \nCommittee Chair: Nikil Dutt \nAbstract: \nOver the last few decades\, chip performance has increased steadily due to continuous and aggressive technology scaling. However\, it leaves chips quite vulnerable to several issues at the same time; high power densities in some particular areas spread across a chip might result in hotspots and thermal gradients\, and these can lead to permanent damage to the chip and also can reduce the reliability of the entire system using the chip. As a result\, a large number of dynamic thermal management solutions have been proposed in recent years for use in multi-core architectures\, and the accurate temperature information over the entire chip area has become indispensable especially for fine-grain dynamic thermal management solutions. Naturally\, on-chip thermal sensors came to play an important role in providing the accurate information on the temperature distribution of a chip\, but there still remain some issues regarding the allocation of on-chip thermal sensors; due to power\, area and routing issues\, it is preferable to limit the number of on-chip thermal sensors on a die\, and their placement needs to be considered carefully in order to increase the accuracy of full-chip thermal profile reconstruction especially when just a small number of sensors can be implemented; due to the limited reading accuracy of low-power\, small-sized on-chip thermal sensors\, it would be better to have some way to improve their reading accuracy. \nIn this work\, an issue will be firstly addressed regarding how to improve the reading accuracy of a low-power\, small-sized on-chip thermal sensor such as Ring-Oscillator (RO) based sensors at runtime on a software level. Secondly\, a question of how to allocate a proper number of sensors on a die in order to get the accurate full-chip scale thermal information on the run is addressed. Additionally\, a temperature-aware routing for global interconnects to minimize the delay and also to reduce the probability of chip failure due to electromigration is presented at the end.
URL:https://www.cecs.uci.edu/event/temperature-aware-design-for-socs-using-thermal-gradient-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150507T150000
DTEND;TZID=America/Los_Angeles:20150507T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14430-1431010800-1431014400@www.cecs.uci.edu
SUMMARY:Resilient On-Chip Memory Design in the Nano Era
DESCRIPTION:Final Defense – Abbas Banaiyanmofrad\n\nMay 20\, 2015\n3pm – 5pm\nDonald Bren Hall 3011 Conference Room \nCommittee:\nNikil Dutt (Chair)\, Alex Nicolau\, Alex Veidenbaum \nTitle:\nResilient On-Chip Memory Design in the Nano Era \nAbstract:\nAggressive technology scaling in the nano-scale regime makes chips more susceptible to failures. This causes multiple reliability challenges in the design of modern chips\, including manufacturing defects\, wear-out\, and parametric variations. By increasing the number\, amount\, and hierarchy of on-chip memory blocks in emerging computing systems\, the reliability of the memory sub-system becomes an increasingly challenging design issue. Existing resilient memory design schemes are unable to effectively address the key features of scalability\, interconnect-awareness\, and cost-effectiveness for these platforms. In this thesis\, we propose different approaches to address resilient on-chip memory design in computing systems ranging from traditional single-core processors to emerging many-core platforms. We classify our proposed approaches in five main categories: 1) Flexible and low-cost approaches to protect cache memories in single-core processors against permanent faults and transient errors\, 2) Scalable fault-tolerant approaches to protect last-level caches with non-uniform cache access in chip multiprocessors\, 3) Interconnect-aware cache protection schemes in network-on-chip architectures\, 4) Application-aware memory resiliency for approximate computing era\, and 5) System-level design space exploration\, analysis\, and optimization for redundancy-aware on-chip memory resiliency in many-core platforms. ​  \n In summary\, the premise of this thesis is to provide multiple solutions in different layers of system hierarchy targeting a verity of architectures from embedded single-core microprocessors to emerging large many-core platforms to address cost-efficient error-resiliency of on-chip memory components. \n 
URL:https://www.cecs.uci.edu/event/resilient-on-chip-memory-design-in-the-nano-era/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150416T150000
DTEND;TZID=America/Los_Angeles:20150416T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14397-1429196400-1429200000@www.cecs.uci.edu
SUMMARY:Self-stabilizing Java: Tool Support for Building Robust Software
DESCRIPTION:Name: Yong hun EomDate: April 15\, 2015\nTime: 10:00am\nLocation: EH 2430\nCommittee Chair: Professor Demsky\nCommittee members: Prof. Pai Chou and Prof. Rainer Doemer \nTitle: Self-stabilizing Java: Tool Support for Building Robust Software \nAbstract:\nDeveloping robust software systems remains an open research problem. The\ncurrent approaches for improving software reliability mainly focus on\nminimizing the number of software bugs through formal verification or\nextensive testing. Despite such efforts\, it is common that unexpected\nsoftware bugs corrupt a program’s state and cause systems to fail. \nThe motivation for this research is to embrace the fact that it is\ndifficult to guarantee that software is error-free. We present\nSelf-stabilizing Java (SJava) that instead checks that a program\nself-stabilizes. Self-stabilizing programs automatically recover to the\ncorrect state from the corrupted state caused by software bugs and other\nsources. A number of applications are inherently self-stabilizing—such\nprograms typically overwrite all non-constant data with new input data. \nWe have developed a type system and static analyses that together check\nwhether program executions eventually transition from incorrect states\nto the correct state. We combine this with a code-generation strategy\nthat ensures that a program continues executing long enough to\nself-stabilize. Furthermore\, in order to lower the burden of type\nannotations\, we present an annotation inference algorithm that\nautomatically derives an initial set of annotations. \nOur experience using SJava indicates that our system successfully\nchecked that several benchmarks were self-stabilizing and effectively\ninferred annotations for our benchmarks.
URL:https://www.cecs.uci.edu/event/self-stabilizing-java-tool-support-for-building-robust-software/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150202T150000
DTEND;TZID=America/Los_Angeles:20150202T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14421-1422889200-1422892800@www.cecs.uci.edu
SUMMARY:Formal Analysis of Electronic System Level Models using Satisfiability Modulo Theories and Automata Checking
DESCRIPTION:Name:  Che-Wei Chang\nDate/Time:  Wednesday\, January 28\,2015\, 9:00am \nLocation:  EH 3404 \nCommittee Chair: Rainer Doemer \nCommittee Member: Daniel Gajski \nCommittee Member: Pai Chou \nAbstract:  \nFor a system-level design which may be composed of multiple processing elements running\n        in parallel\, various kinds of unwanted consequences may happen if the system\n        is constructed carelessly. For example\, deadlock may happen if improper execution\n        order and communication between processing elements is used in the system. Another\n        problem which may be caused by the concurrent execution is race condition\, as\n        shared variables in the system-level model could be accessed by multiple concurrent\n        threads in parallel. Those unwanted behaviors definitely have negative influence on\n        the functionality of the system. Furthermore\, the functionality is not the only concern\n        in system design as timing constraints are critical as well. If the system cannot\n        finish the job within timing constraints\, it is still considered an unwanted design. To\n        address this issue\, we propose two formal analysis approaches in this dissertation to\n        analyze three types of properties we discussed above\, which are\n        1). liveness\,\n        2). satisfiability of timing constraint\, and\n        3). May-Happen-in-Parallel access.\n        These two approaches are based on Satisfiability Modulo Theories (SMT) and UPPAAL\n        automaton model respectively. We run these two approaches on our in-house\n        system models\, including a JPEG encoder\, MP3 decoder\, AMBA AHB and CAN\n        bus protocol models. The experimental results show our approaches are capable of\n        analyzing those properties meeting our expectation within reasonable analysis time.
URL:https://www.cecs.uci.edu/event/formal-analysis-of-electronic-system-level-models-using-satisfiability-modulo-theories-and-automata-checking/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140923T150000
DTEND;TZID=America/Los_Angeles:20140923T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14418-1411484400-1411488000@www.cecs.uci.edu
SUMMARY:Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture
DESCRIPTION:Title:� Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture\nSpeaker:� Francis Caster II \nLocation/Time:� September 23\, 2014\, 3PM\nCommittee Members:\nPayam Heydari\nFilippo Capolino\nH. Kumar Wickramasinghe\nAbstract: Multi-pixel passive imaging arrays are presently fabricated in expensive processes with low integration levels. Imaging arrays designed in inexpensive processes with higher levels of integration would result in cheaper larger arrays. The objective of this work is twofold: 1) to develop a highly integrated silicon-based passive imaging receiver integrating the entire receiver frontend from antenna to detector; and 2) to develop a highly scalable architecture for use in focal plane arrays of arbitrary dimensions\, incorporating new features to address large-array issues while retaining the pixel density of conventional focal plane arrays. A new area-efficient beam-steerable imaging array receiver architecture suitable to integrated circuit realization up to sub-THz frequencies is presented. A direct-detection-based receiver array utilizing the proposed architecture is designed and implemented in an advanced 0.18�m BiCMOS process. The receiver chip achieves a peak measured coherent responsivity of 1\,150MV/W\, a measured incoherent responsivity of 1\,000MV/W\, a minimum NEP of 0.28fW/sqrtHz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45K with a 20ms integration time. The proposed architecture uses a new concept of spatial-overlapping super-pixels which results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2�2 window averaging function in the RF domain\, (4) the ability to compensate for the systematic time delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5) the ability to compensate for mutual coupling effects among the array elements.
URL:https://www.cecs.uci.edu/event/design-analysis-and-implementation-of-an-area-efficient-beam-steerable-sub-terahertz-imaging-receiver-array-architecture/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14416-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor Platforms
DESCRIPTION:Title:  Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor  Platforms \nSpeaker:  Kyoungwon Kim \nDate/Time:  August 28\, 2014\, 2:oopm \nLocation:  Engineering Hall 3206 \nCommittee Members:Daniel Gajski (Chair)Tony Givargis Rainer Doemer \nAbstract:  Embedded system designers continuously face a twofold challenge handling the ever-increasing complexity of design and meeting the ever-shrinking time-to-market timeline. To meet such a challenge\, the system design paradigm has shifted to platform-based design characterized by intensive use of software and aggressive reuse of verified components. More and more designs are turning to heterogeneous platforms to meet design constraints in multiple criteria. However the use of such and heterogeneity generates more challenges for platform-based design. To address the challenges\, system designers must utilize system-level methodologies for specification and design. Here the designers begin the design process by coming up with a computation model that captures the behavior of the system. The computation model is successively refined down to the structural model in the system level. In each refinement\, the designers explore the design space. The design space comprises a set of alternatives concerning hardware/software partitioning\, platform selection\, and mapping. The design space is huge\, however\, necessitating the automation of its exploration. The platform is very often fixed regarding either availability or legacy reasons\, making mapping crucial. This dissertation focuses on the automatic mapping of the computation model for the given heterogeneous platform. This dissertation presents a new automatic mapping technique based on the input computation model. The proposed technique consists of two separate phases: initial mapping and improvement driven by cycle-approximate estimation. Existing mapping techniques depend on early estimation so a dilemma arises from the fact that cycle-approximate estimation cannot precede mapping. The dilemma can be gotten around by our performing initial mapping based on rough estimation and then making iterative improvements based on cycle-approximate estimation. While earlier work has been domain specific\, the mapping techniques in the proposed work are driven by a general computation model that includes hierarchy\, state transitions\, dynamic data-oriented behaviour\, and imperative languages\, while previous work is domain specific.The proposed work also addresses mapping with an awareness of general hierarchy in pipelined applications. The size of the design space explored is limited by the speed of cycle-approximate estimation. Orders of magnitude faster than Simulation-based cycle-approximate estimation\, the new trace-driven estimation presented in this disseration is cycle-approximate and applicable to both software and hardware. The new trace-driven estimation assumes that the execution path of each task depends on data only. As the trace-driven estimation handles a portion of applications\, it complements the existing simulation-based cycle-approximate estimation. We have applied the proposed mapping techniques to multiple multimedia applications and the techniques outperformed in terms of execution time the competitors by proportions ranging from 23.3% through 36.3%.
URL:https://www.cecs.uci.edu/event/computation-model-based-automatic-design-space-exploration-for-heterogeneous-multiprocessor-platforms/
CATEGORIES:PhD Defenses
END:VEVENT
END:VCALENDAR