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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20200529T140000
DTEND;TZID=America/Los_Angeles:20200529T150000
DTSTAMP:20231011T190957Z
CREATED:20231011T190957Z
LAST-MODIFIED:20231011T190957Z
UID:14579-1590760800-1590764400@www.cecs.uci.edu
SUMMARY:Advancing Compiler and Simulator Techniques for Highly Parallel Simulation of Embedded Systems
DESCRIPTION:Name: Zhongqi Cheng\nChair: Prof. Rainer Doemer \nDate: May 29th\, 2020 \nTime: 02:00 PM \nLocation:  Zoom \nCommittee: Rainer Doemer (Chair)\, Prof. Mohammad Al Faruque and Prof. Aparna Chandramowlishwaran \nTitle: “Advancing Compiler and Simulator Techniques for Highly Parallel Simulation of Embedded Systems” \nAbstract: \nAs an Electronic System Level (ESL) design language\, the IEEE SystemC standard is widely used for testing\, validation and verification of embedded system models. Discrete Event Simulation (DES) has been used for decades as the default SystemC simulation semantic. However\, due to the sequential nature of DES\, Parallel DES has recently gained an increasing amount of attention for performing high speed simulations on parallel computing platforms. To further exploit the parallel computation power of modern multi- and many-core platforms\, Out-of-order Parallel Discrete Event Simulation (OoO PDES) has been proposed. In OoO PDES\, threads comply with a partial order such that different simulation threads may run in different time cycles to increase the parallelism of execution. The Recoding Infrastructure for SystemC (RISC) has been introduced as a tool flow to fully support OoO PDES. \nTo preserve the SystemC semantics under OoO PDES\, a compiler based approach statically analyzes the race conditions in the input model. However\, there are severe restrictions: the source code for the input design must be available in one file\, which does not scale. This disables the use of Intellectual Property (IP) and hierarchical file structures. In this dissertation\, we propose a partial-graph based approach to scale the static analysis to support separate files and IP reuse. Specifically\, the Partial Segment Graph (PSG) data structure is proposed and is used to abstract the behaviours and communication of modules within a single translation unit. These partial graphs are combined at top level to reconstruct the complete behaviors and communication of the entire model. \nWe also propose new algorithms to support the static analysis for modern SystemC TLM-2.0 standard. SystemC TLM-2.0 is widely used in industrial ESL designs for better interoperability and higher simulation speed. However\, it is identified as an obstacle for parallel SystemC simulation due to the disappearance of channels. To solve the problem\, we propose a compile time approach to statically analyze potential conflicts among threads in SystemC TLM-2.0 loosely- and approximately-timed models. A new Socket Call Path (SCP) technique is introduced which provides the compiler with socket binding information for precise static analysis. Based on SCP\, an algorithm is proposed to analyze entangled variable pairs for automatic and accurate conflict analysis. \nBesides the works on the compiler side\, we focus as well on increasing the simulation speed of OoO PDES. We observe that the granularity of the Segment Graph (SG) data structure used in static analysis has a high impact on OoO PDES. This motivates us to propose a set of coding guidelines for the RISC users to properly refine their SystemC model for a higher simulation speed. \nFurthermore\, in this dissertation\, an algorithm is proposed to optimize directly the event delivery strategy in OoO PDES. Event delivery in OoO PDES was very conservative\, which often postponed the execution of waiting threads due to unknown future behaviors of the SystemC model\, and in turn became a bottleneck of simulation speed. The algorithm we propose takes advantage of the prediction of future thread behaviors\, and therefore allows waiting threads to resume execution earlier\, resulting in significantly increased simulation speed. \nTo summarize\, the contributions of this dissertation include: 1) a scalable RISC tool flow for statically analyzing and protecting 3rd party IPs in models with multiple files\, 2) an advanced static analysis approach for modern SystemC TLM-2.0 models\, 3) a set of coding guidelines for RISC users to achieve higher simulation speed\, and 4) a more efficient event delivery algorithm in OoO PDES scheduler using prediction information. \nTogether\, these compiler and simulator advances enable OoO PDES for larger and modern model simulation and thus improve the design of embedded systems significantly\, leading to better devices at lower cost in the end. \n 
URL:https://www.cecs.uci.edu/event/advancing-compiler-and-simulator-techniques-for-highly-parallel-simulation-of-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20200310T093000
DTEND;TZID=America/Los_Angeles:20200310T103000
DTSTAMP:20231011T190957Z
CREATED:20231011T190957Z
LAST-MODIFIED:20231011T190957Z
UID:14578-1583832600-1583836200@www.cecs.uci.edu
SUMMARY:Design and Implementation of Robust Full-Duplex Wireless Network
DESCRIPTION:Name: Sergey Shaboyan\nChair: Prof. Ahmed Eltawil \nDate: March 10th\, 2020 \nTime: 09:30 AM \nLocation:  EH 3206 \nCommittee: Prof. Ahmed Eltawil (Chair)\, Prof. Ender Ayanoglu\, Prof. Zhiying Wang \nTitle: “Design and Implementation of Robust Full-Duplex Wireless Network” \nAbstract: \nRecently Full-Duplex (FD) communication has gained significant interest due to demonstrable increase in throughput and spectral efficiency. Conventional Half-duplex (HD) communication systems use either time-duplexing or frequency-duplexing to avoid self-interference. In contrast\, full-duplex systems transmit and receive simultaneously on the same frequency band\, thus optimally utilizing available resources. The main challenge in FD systems is managing the self-interference (SI) signal at each node\, which is typically orders of magnitude larger than the intended signal of interest (SOI). To achieve sufficient SI suppression\, FD systems rely on cancellation across multiple domains such as spatial\, analog\, and digital. However\, number of practical\, FD specific challenges arise impacting quality of service\, when at least one node in a network operates in full-duplex mode. \nIn this thesis\, we consider practical issues of wireless networks containing a full-duplex node. The ultimate goal of this work is to design and implement real-time\, end-to-end networks consisting of at least one FD node that is capable of improving network performance under limited available bandwidth constraint. First\, we identify synchronization issues in a network consisting of a full-duplex base station communicating with half-duplex nodes. Novel synchronization techniques specific for full-duplex networks are proposed that allow compensation of synchronization errors in time and frequency. The proposed techniques are implemented and tested experimentally on a real-time full-duplex wireless network. Second\, we characterize the dynamic environment impact on the received self-interference in the FD system\, which is equipped with a reconfigurable antenna as a passive SI suppression mechanism. The self-interference channel delay profile is measured using the FD system operating on 5MHz\, 10MHz\, and 20MHz bandwidths. The measured channel profiles collected under suppressing and non-suppressing antenna patterns are compared\, and channel changes in static\, as well as dynamic environments\, are highlighted. We then statistically model the SI channel by performing probability distribution fitting to SI channel data. Third\, the thesis proposes a Wi-Fi compliant self-interference active cancellation technique for amplify and forward\, as well as decode and forward full-duplex relays. Finally\, we design and implement an end-to-end wireless network extended with the aid of a custom-designed amplify and forward full-duplex relay. We then analyze the relay coverage limitation under the stability and transmit power constraints. The network performance is analyzed as a function of relay location for constant gain and constant transmit power modes\, consequently suggesting optimal relay location that will maximize signal to noise plus interference ratio (SINR) at the destination node. We evaluate the overall network performance by simulation\, as well as experimentally in outdoor/indoor environments.
URL:https://www.cecs.uci.edu/event/design-and-implementation-of-robust-full-duplex-wireless-network/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20200220T100000
DTEND;TZID=America/Los_Angeles:20200220T110000
DTSTAMP:20231011T190957Z
CREATED:20231011T190957Z
LAST-MODIFIED:20231011T190957Z
UID:14577-1582192800-1582196400@www.cecs.uci.edu
SUMMARY:Novel Monitoring\, Detection\, and Optimization Techniques for Neurological Disorders
DESCRIPTION:Name: Seyede Mahya Safavi\nChair: Prof. Pai Chou \nDate: February 20th\, 2020 \nTime: 10:00 AM \nLocation:  EH 3404 \nCommittee: Prof. Pai Chou (Chair)\, Prof. Beth Lopour\, Prof. Phillip Sheu \nTitle: “Novel Monitoring\, Detection\, and Optimization Techniques for Neurological Disorders” \nAbstract: \nThe advancement in chronically implanted neural recording devices has led to advent of assisting devices for rehabilitation and restoring lost sensorimotor functions in patients suffering from paralysis. Electrocorticogram (ECoG) signal can record high-Gamma sub-band activity known to be related to hand movements. In the first part of this work\, we Propose a finger movement detection technique based on ECoG source localization. In fact\, the finger flexion and extension are originating in slightly different areas of motor cortex. The origin of the brain activity is used as the distinctive feature for decoding the finger movement. \nThe real-time implementation of brain source localization is challenging due to extensive iterations in the existing solutions. In the second part of this work\, we have proposed two techniques to reduce the computational complexity of the Multiple Signal Classification (MUSIC) algorithm. First the cortex surface is parsed into several regions. Next\, a novel nominating procedure will pick a number of regions to be searched for brain activity. In the second step\, an electrode selection technique based on the Cramer-Rao bound of the errors is proposed to select the best set of an arbitrary number of electrodes. The proposed techniques lead to 90% reduction in computational complexity while maintaining a good concordance in terms of localization error compared to regular MUSIC algorithm. \nEpilepsy is a neurological disorder with multiple comorbid conditions including cardiovascular and respiratory disorders. The cardiovascular imbalance is of great importance since the mechanisms of Sudden Unexpected Death in Epilepsy (SUDEP) is still unknown. The ictal tachycardia is the most well-known cardiac imbalance during the seizure. In the third part of this dissertation\, we used an optical sensor called photoplethysmogram (PPG) to investigate the variations in ictal blood flow in limbs. Six different features related to hemodynamics were derived from PPG pulse morphology. A consistent pattern of ictal change was observed across all the subjects/seizures. These variations suggest an increase in vascular resistance due to an increase in sympathetic tone. The timing analysis of the PPG features revealed some PPG feature variations can precede the ictal tachycardia by 50 seconds. These features were used to train a neural network based on Long Short Term Memory LSTM architecture for automatic seizure detection. We were able to reduce the False Alarm rate by 50% compared to other heart rate variability based detectors.
URL:https://www.cecs.uci.edu/event/novel-monitoring-detection-and-optimization-techniques-for-neurological-disorders/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20200206T093000
DTEND;TZID=America/Los_Angeles:20200206T103000
DTSTAMP:20231011T190957Z
CREATED:20231011T190957Z
LAST-MODIFIED:20231011T190957Z
UID:14575-1580981400-1580985000@www.cecs.uci.edu
SUMMARY:Efficient Offline and Online Training of Memristive Neuromorphic Hardware
DESCRIPTION:Name: Mohammed Fouda\nChair: Prof. Ahmed Eltawil \nDate: February 6th\, 2020 \nTime: 9:30 AM \nLocation:  EH 3206 \nCommittee: Ahmed Eltawil (Chair)\, Prof. Fadi Kurdahi\, Prof. Nikil Dutt\, Prof. Emre Neftci \nTitle: “Efficient Offline and Online Training of Memristive Neuromorphic Hardware” \nAbstract: \nBrain-inspired neuromorphic systems have witnessed rapid development over the last decade from both algorithmic and hardware perspectives. Neuromorphic hardware promises to be more energy- and speed- efficient as compared to traditional Von-Neumann architectures. Thanks to the recent progress in solid-state devices\, different nanoscale-nonvolatile memory devices\, such as RRAMs (memristors)\, STT-RAM and PCM\, support computations based on mimicking biological synaptic response. The most important advantage of these devices is their ability to be sandwiched between interconnect wires creating crossbar array structures that are inherently able to perform matrix-vector multiplication (MVM) in one step. Despite the great potential of RRAMs\, they suffer from numerous nonidealities limiting the performance\, including\, high variability\, asymmetric and nonlinear weight update\, endurance\, retention and stuck at fault (SAF) defects in addition to the interconnect wire resistance that creates sneak paths. This thesis will focus on the application of RRAMs for neuromorphic computation while accounting for the impact of device nonidealities on neuromorphic hardware. \n\n\n\n\nIn this thesis\, we propose software-level solutions to mitigate the impact of nonidealities\, that highly affect the offline (ex-situ) training\, without incorporating expensive SPICE or numerical simulations. We propose two techniques to incorporate the effect of sneak path problem during training\, in addition to the device’s variability\, with negligible overhead. The first technique is inspired by the impact of the sneak path problem on the stored weights (devices’ conductances) which we referred to as the mask technique. This mask is element-wise multiplied by the weights during the training. This mask can be obtained from measured weights of fabricated hardware. The other solution is a neural network estimator which is trained by our SPICE-like simulator. The test validation results\, done through our SPICE-like framework\, show significant improvement in performance\, close to the baseline BNNs and QNNs\, which demonstrates the efficiency of the proposed methods. Both techniques show the high ability to capture the problem for multilayer perceptron networks for MNIST dataset with negligible runtime overhead. In addition\, the proposed neural estimator outperforms the mask technique for challenging datasets such as CIFAR10. Furthermore\, other nonidealities such as SAF defects and retention are evaluated. \nWe also develop a model to incorporate the stochastic asymmetric nonlinear weight update in online (in-situ) training. We propose two solutions for this problem; 1) a compensation technique which is tested on a small scale problem to separate two Laplacian mixed sources using online independent component analysis. 2) stochastic rounding and is tested on a spiking neural network with deep local learning dynamics showing only a 1~2% drop in the baseline accuracy for three different RRAM devices. We also propose Error-triggered learning to overcome the limited endurance problem with only 0.3% and 3% drop in the accuracy for N-MNIST and DVSGesture datasets with around 33X and 100X reduction in the number of writes\, respectively. \nFinally\, the prospects of this neuromorphic hardware are discussed to develop new algorithms with the existing resistive crossbar hardware including its nonidealities.
URL:https://www.cecs.uci.edu/event/efficient-offline-and-online-training-of-memristive-neuromorphic-hardware/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20191011T150000
DTEND;TZID=America/Los_Angeles:20191011T160000
DTSTAMP:20231011T190904Z
CREATED:20231011T190900Z
LAST-MODIFIED:20231011T190904Z
UID:14567-1570806000-1570809600@www.cecs.uci.edu
SUMMARY:Towards Engineering Computer Vision Systems: From Web to FPGAs
DESCRIPTION:Final Defense – Sajjad Taheri \n\n\nDate: August 26\, 2019\nTime: 2:00 pm \n\nLocation: Donald Bren Hall 4011 \n\n\nCommittee: Alex Nicolau(chair)\, Alex Veidenbaum(co-chair)\, Nikil Dutt \n\n\nTitle: Towards Engineering Computer Vision Systems: From Web to FPGAs\n\n\n\nAbstract:\n\nComputer vision has many applications that impact our daily lives\, such as automation\, entertainment\, healthcare\, etc. However\, computer vision is very challenging. This is in part due to intrinsically difficult nature of the problem and partly due to the complexity and size of visual data that need to be processed. To be able to deploy computer vision in many practical use cases\, sophisticated algorithms and efficient implementations are required. In this dissertation\, we consider two platforms that are suitable for computer vision processing\, yet they were not easily accessible to algorithm designers and developers: The Web and FPGA-based Accelerators. Through the development of open-source software\, we highlight challenges associated with vision development on each platform and demonstrate opportunities to mitigate them.\n\nThe Web is the world’s most ubiquitous computing platform which hosts a plethora of visual content. Due to historical reasons such as insufficient JavaScript performance and lack of API support for acquiring and manipulating images\, computer vision is not mainstream on the Web. We show that in light of recent web developments such as vastly improved JavaScript performance and addition of APIs such as WebRTC\, efficient computer vision processing can be realized on web clients. Through novel engineering techniques\, we translate a popular open-source computer vision library (OpenCV) from C++ to JavaScript and optimize its performance for the web environment. We demonstrate that hundreds of computer vision functions run in browsers with performance close to their original C++ version.\n\nField Programmable Gate Arrays (FPGA)s are a promising solution to mitigate the computational cost of vision algorithms through hardware pipelining and parallelism while providing excellent power efficiency. However\, an efficient FPGA implementation of vision algorithm requires hardware design expertise and a considerable amount of engineering person-hours. We show how high-level graph-based specifications\, such as OpenVX can significantly improve FPGA design productivity. Since such abstractions exclude implementation details\, different implementation configurations that satisfy various design constraints\, such as performance and power consumption\, can be explored systematically. They also enable a variety of local and global optimizations to apply across the algorithms.
URL:https://www.cecs.uci.edu/event/towards-engineering-computer-vision-systems-from-web-to-fpgas/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190826T150000
DTEND;TZID=America/Los_Angeles:20190826T160000
DTSTAMP:20231011T190904Z
CREATED:20231011T190859Z
LAST-MODIFIED:20231011T190904Z
UID:14565-1566831600-1566835200@www.cecs.uci.edu
SUMMARY:Event Detection and Estimation Using Distributed Population Owned Sensors
DESCRIPTION:Name: Ahmed Mokhtar Nagy Ibrahim\nChair: Prof. Ahmed Eltawil \nDate: August 7th\, 2019 \nTime: 1:00 pm \nLocation:  EH 2210 – EECS Chair’s Conference Room \nCommittee: Ahmed Eltawil(Chair)\, Ender Ayanoglu\, and Lee Swindlehurst \nTitle:”Event Detection and Estimation Using Distributed Population Owned Sensors ” \nAbstract:\nSmart phones are an indispensable tool in modern day-to-day life. Their widespread use has spawned numerous applications targeting diverse domains such as bio-medical\, environment sensing and infrastructure monitoring. In such applications\, the accuracy of the sensors at the core of the system is still questionable\, since these devices are not originally designed for high accuracy sensing purposes. In this thesis\, we investigate the accuracy limits of one of the commonly used sensors\, namely\, a smart phone accelerometer. As a use case\, we focus on utilizing smart phone accelerometers in structural health monitoring (SHM). Using the already deployed network of distributed citizen-owned sensors is considered a cheap alternative to standalone sensors. These devices can capture floors vibration during disasters\, and consequently compute the instantaneous displacement of each floor. Hence\, damage indicators defined by government standards such as peak relative displacement can be estimated. In this work\, we study the displacement estimation accuracy and propose a zero-velocity update (ZUPT) method for noise cancellation. Theoretical derivation and experimental validation are presented\, and we discuss the impact of sensor error on the achieved building classification accuracy. Moreover\, in spite of the presence of sensor error\, SHM systems can be resilient by adopting machine learning. Several algorithms such as support vector machine (SVM)\, K-nearest neighbor (KNN) and convolutional neural network (CNN) are adopted and compared. Techniques for addressing noise levels are proposed and the results are compared to regular noise cancellation techniques such as filtering. \nFinally\, since most previous work focused on modelling the sensor chip error itself\, we study other sources of error such as sampling time uncertainty which is introduced by the device operating system (OS). That type of error can be considered a major contributor to the overall error\, specially for sufficiently large signals. Hence\, we propose a novel smart device accelerometer error model that includes the traditional additive noise as well as sampling time uncertainty errors. The model is validated experimentally using shake table experiments\, and maximum likely-hood estimation (MLE) is used to estimate the model parameters. Moreover\, we derive the Cramer-Rao lower bound (CRLB) of acceleration estimation based on the proposed model.
URL:https://www.cecs.uci.edu/event/event-detection-and-estimation-using-distributed-population-owned-sensors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190812T150000
DTEND;TZID=America/Los_Angeles:20190812T160000
DTSTAMP:20231011T190852Z
CREATED:20231011T190846Z
LAST-MODIFIED:20231011T190852Z
UID:14559-1565622000-1565625600@www.cecs.uci.edu
SUMMARY:Cooperative Power and Resource Management for Heterogeneous Mobile Architectures
DESCRIPTION:Name: Chenying Hsieh\n\nDate: Wednesday Aug 7\, 2019 \n\n\n\n\n\n\nTime: 2:00 pm\n\nLocation: Donald Bren Hall 4011\n\nCommittee: Nikil Dutt (Chair)\, Tony Givargis\, and Ardalan Amiri Sani\n\nTitle: Cooperative Power and Resource Management for Heterogeneous Mobile Architectures\n \nAbstract:\n\n\n\n\n\n\nHeterogeneous architectures have been ubiquitous in mobile system-on-chips (SoCs). The demand from different application domains such as games\, computer vision and machine learning which requires massive parallelism of computation has driven the integration of more accelerators into mobile SoCs to provide satisfactory performance energy-efficiently.These on-chip computing resources typically have their individual runtime systems including: (1) a software governor: continuously monitors hardware utilization and makes decisions of trade-off between performance and power consumption. (2) software stack: allows application developers to program the hardware for general purpose computation and perform memory management and profiling. As computation of mobile applications may demand all sorts of combinations of computing resources\, we identify two problems: (1) individual runtime can often lead to poor performance-power trade-off or inefficient utilization of computing resources. (2) existing approaches fail to schedule subprograms among different computing resources and further lose the opportunity to avoid resource contention to gain better performance.\n\nTo address these issues\, we propose a holistic approach to coordinate different runtime regrading application performance and energy efficiency in this dissertation. We first present MEMCOP\, a memory-aware collaborative CPU-GPU governor that considers both the memory access footprint as well as the CPU/GPU frequency to improve energy efficiency of high-end mobile game workloads by performing dynamic voltage and frequency scaling (DVFS). Second\, We present a case study executing a mix of popular data-parallel workloads such as convolutional neural networks (CNNs)\, computer vision filters and graphics rendering kernels on mobile devices\, and show that both performance and energy consumption of mobile platforms can be improved by synergistically deploying these underutilized compute resources. Third\, we present SURF: a self-aware unified runtime framework for parallel programs on heterogeneous mobile architectures. SURF supports several heterogeneous parallel programming languages (including OpenMP and OpenCL)\, and enables dynamic task-mapping to heterogeneous resources based on runtime measurement and prediction.The measurement and monitoring loop enables self-aware adaptation of run-time mapping to exploit the best available resource dynamically.\n\nWe implemented all the software components on real-world mobile SoCs and evaluate our proposed approaches with mobile games and mix of parallel benchmarks and CNN applications accordingly.
URL:https://www.cecs.uci.edu/event/cooperative-power-and-resource-management-for-heterogeneous-mobile-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190806T150000
DTEND;TZID=America/Los_Angeles:20190806T160000
DTSTAMP:20231011T190852Z
CREATED:20231011T190846Z
LAST-MODIFIED:20231011T190852Z
UID:14558-1565103600-1565107200@www.cecs.uci.edu
SUMMARY:Low-Power Integrated Circuits For Biomedical Applications
DESCRIPTION:Title: “Low-Power Integrated Circuits For Biomedical Applications”\nName: Karimi Bidhendi\, Alireza \nChair: Professor Payam Heydari \nDate: August 6\, 2019 \nTime: 1 pm \nLocation: Calit2\,  Room 3008 \nAbstract: \nWith thousands new cases of spinal cord injury reported everyday\, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs\, such a state severely deteriorates a patients quality of life and may even lead to additional medical conditions. Therefore\, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient’s brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals\, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts\, having high spatial resolution and signal to noise ratio\, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore\, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted. \nTo implement a fully implantable system\, low-power and miniaturized electronics are needed to reduce heat generation\, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system’s components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system\, namely\, ultra low-power brain signal acquisition front-ends\, a low-power and inductorless MedRadio transceiver\, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillators generate the reference signal for other system components such as analog to digital converters. Novel techniques to improve important performance parameters (power consumption\, low noise operation and interference resilience) have been introduced. Electrical\, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design.
URL:https://www.cecs.uci.edu/event/low-power-integrated-circuits-for-biomedical-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190522T150000
DTEND;TZID=America/Los_Angeles:20190522T160000
DTSTAMP:20231011T190852Z
CREATED:20231011T190846Z
LAST-MODIFIED:20231011T190852Z
UID:14556-1558537200-1558540800@www.cecs.uci.edu
SUMMARY:Data-Driven Modeling of Cyber-Physical Systems using Side-Channel Analysis
DESCRIPTION:Title: “Data-Driven Modeling of Cyber-Physical Systems using Side-Channel Analysis”\nName: Sujit Rokka Chhetri \nDate: May 20\, 2019 \nTime: 3:00 PM \nLocation: EH 5200 \nCommittee: Prof. Mohammad Al Faruque (Chair)\, Prof. Pramod Khargonekar\, Prof. Fadi Kurdahi \nAbstract: \nCyber-Physical System consists of the integration of computational components in the cyber-domain with the physical-domain processes. In cyber-domain\, embedded computers and networks monitor and control the physical processes\, and in the physical-domain the sensors and actuators aid in interacting with the physical world. This interaction between the cyber and physical domain brings unique modeling challenges one of which includes the integration of discrete models in cyber-domain with the continuous physical domain processes. However\, the same cyber-physical interaction also opens new opportunities for modeling. For example\, the information flow in the cyber-domain manifests physically in the form of energy flows in the physical domain. Some of these energy flows unintentionally provide information about the cyber-domain through the side-channels. \nIn this thesis\, the extensive analysis of the side-channels (such as acoustic\, magnetic\, thermal\, power and vibration) of the cyber-physical system is performed. Based on this analysis data-driven models are estimated. These models are then used to perform security vulnerability analysis (for confidentiality and integrity)\, whereby\, new attack models are explored.  Furthermore\, the data-driven models are also utilized to create a defensive mechanism to minimize the information leakage from the system and to detect attacks to the integrity of the system. The cyber-physical manufacturing systems are taken as use cases to demonstrate the applicability of the modeling approaches. \nFinally\, the side-channel analysis is also performed to aid in modeling digital twins of the cyber-physical systems. Specifically\, a novel methodology to utilize low-end sensors to analyze the side-channels and build the digital twins is proposed. These digital twins are used to capture the interaction between the cyber-domain and the physical domain of the manufacturing systems\, and aid in process quality inference and fault localization. Using side-channels these digital twins are kept up-to-date\, which is one of the fundamental requirements for building digital twins.
URL:https://www.cecs.uci.edu/event/data-driven-modeling-of-cyber-physical-systems-using-side-channel-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190227T150000
DTEND;TZID=America/Los_Angeles:20190227T160000
DTSTAMP:20231011T190843Z
CREATED:20231011T190828Z
LAST-MODIFIED:20231011T190843Z
UID:14548-1551279600-1551283200@www.cecs.uci.edu
SUMMARY:Cyber-Physical Systems Approach to Irrigation Systems
DESCRIPTION:Title: “Cyber-Physical Systems Approach to Irrigation Systems”\nName: Davit Hovhannisyan \nDate: March 5\, 2019 \nTime: 4:00PM \nLocation: EH 3206  (CECS conference room) \nCommittee:  Prof. Fadi Kurdahi (Chair)\, Prof. Ahmed Eltawil\, Prof. Mohammad Al Faruque \nAbstract: \nSemiconductor industry has successfully brought silicon technology to price point that it is accessible for application domains such as irrigation systems\, which wastefully utilizes 70% of all fresh water. Moreover\, worldwide fresh water resources will soon reach a deficit due to ever growing demand\, while the state of the art precision irrigation systems utilize sophisticated water delivery drip lines\, yet are only controlled at source by the gut of the end user. This work demonstrates that scientific foundation of cyber-physical systems can be used to design automated\, distributed and intelligent precision irrigation systems that improve irrigation efficiency. Thus\, this work explores and analyzes in depth the cross section of irrigation practices and cyber-physical systems knowledge to show a path toward a successful adaptation of silicon technology that solves one of the greatest challenges of the 21st century\, the fresh water scarcity. To that end\, this work presents contributions that complete a novel vision for next generation precision irrigation systems\, which can be grouped into three main thrusts: (1) circuit inspired models for irrigation system components and scheduling strategies by analogy method\, (2) CPS approach based (a) design methodology capable of comparing irrigation controllers\, (b) simulation tools and software for analyzing the distributed behavior of the specialized irrigation controllers\, (c) topology adaptation technique that utilizes multi-graphs to mine the hydro-wireless topology of the IoT controllers\, and (d) a distributed controller implementation with novel energy harvesting and low power support for irrigation controllers and sensors\, (3) overhead vision solutions for health and growth monitoring. The observations\, analysis and insight from experimental studies were in collaboration with Rancho California Water District\, growers and practitioners.
URL:https://www.cecs.uci.edu/event/cyber-physical-systems-approach-to-irrigation-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20181128T150000
DTEND;TZID=America/Los_Angeles:20181128T160000
DTSTAMP:20231011T190843Z
CREATED:20231011T190827Z
LAST-MODIFIED:20231011T190843Z
UID:14546-1543417200-1543420800@www.cecs.uci.edu
SUMMARY:Control System Design Automation Using Reinforcement Learning
DESCRIPTION:Title: “Control System Design Automation Using Reinforcement Learning”\nName: Hamid Mirzaei \nDate: Tuesday\, November 20\, 2018 \nTime: 1:00 p.m. \nLocation: Donald Bren Hall 3011 \nCommittee: Professor Tony Givargis (Chair)\, Professor Eli Bozorgzadeh\, Professor Ian Harris \nAbstract: \n\n\n\n\n\n\n\n\n\nConventional control theory has been used in many application domains with great success in the past decades. However\, novel solutions are required to cope with the challenges arising from complex interaction of fast growing cyber and physical systems. Specifically\, integration of classical control methods with Cyber-Physical System (CPS) design tools is a non-trivial task since those methods have been developed to be used by human expert and are not intended to be part of an automatic design tool. \n\n\n\n\n\n\n\n\n\n\n\n\nOn the other hand\, the control problems in emerging Cyber-Physical Systems\, such as intelligent transportation and autonomous driving\, cannot be addressed by conventional control methods due to the high level of uncertainty\, complex dynamic model requirements and operational and safety constraints.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nIn this dissertation\, a holistic CPS design approach is proposed in which the control algorithm is incorporated as a building block in the design tool. The proposed approach facilitates the inclusion of physical variability into the design process and reduces the parameter space to be explored. This has been done by adding constraints imposed by the control algorithm.\n\n\nFurthermore\, Reinforcement Learning (RL) as a replacement for convection control solutions are studied in the emerging domain of intelligent transportation systems. Specifically\, dynamic tolling assignments and autonomous intersection management are tackled by the state-of-the-art RL methods\, namely\, Trust Region Policy Optimization and Finite-Difference Gradient Descent. Additionally\, Q-learning is used to improve the performance of an embedded controller using a novel formulation in which cyber-system actions\, such as changing control sampling time\, is combined with the physical action set of the RL agent. Using the proposed approach\, it is shown that the power consumption and computational overhead of the embedded control can be improved.\n\nFinally\, to address the current lack of available physical benchmarks\, an open physical environment benchmarking framework is introduced. In the proposed framework\, various components of a physical environment are captured in a unified repository to enable researchers to define and share standard benchmarks that can be used to evaluate different reinforcement algorithms. They can also share the realized environments via the cloud to enable other groups perform experiments on the actual physical environments instead of currently available simulation-based environments.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n 
URL:https://www.cecs.uci.edu/event/control-system-design-automation-using-reinforcement-learning/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20181016T150000
DTEND;TZID=America/Los_Angeles:20181016T160000
DTSTAMP:20231011T190904Z
CREATED:20231011T190859Z
LAST-MODIFIED:20231011T190904Z
UID:14566-1539702000-1539705600@www.cecs.uci.edu
SUMMARY:An Initial Study of Simple Approaches To Eliminating Out-of-Thin-Air Results
DESCRIPTION:Name: Peizhao Ou\nChair: Prof. Brian Demsky \nDate: Tuesday October 16\, 2018 \nTime: 10am – 12pm \nLocation: CALIT2 Room 3008 \nTitle: An Initial Study of Simple Approaches To Eliminating Out-of-Thin-Air Results \nAbstract:\nEliminating so-called “out-of-thin-air” (OOTA) results is an open problem in many existing programming language memory models including Java\, C\, and C++.  OOTA behaviors are problematic in that they break both formal and informal modular reasoning about program behavior. In spite of many years of research\nefforts\, defining memory model semantics that are easily understood\, allow existing optimizations\, and forbid OOTA results remains an open problem. This thesis explores two simple solutions to this problem that forbid OOTA results. The first solution is targeted towards Java-like languages in which all memory operations may create OOTA executions\, and the second solution is targeted towards C/C++-like memory models in which racing operations are explicitly labeled as atomic operations. Our solutions provide a per-candidate execution criterion that makes it possible to examine a single execution and determine whether the memory model permits the execution. We implemented and evaluated both solutions in the LLVM compiler framework. Our results show that on an ARMv8 processor the first solution has an average overhead of 3.1% and a maximum overhead of 17.6% on the SPEC CPU2006 C/C++ benchmarks\, and that the second solution has no overhead on average and a maximum overhead of 6.3% on 43 concurrent data structures.  The results indicate that these simple approaches to eliminating out-of-thin-air behaviors deserve further consideration.
URL:https://www.cecs.uci.edu/event/an-initial-study-of-simple-approaches-to-eliminating-out-of-thin-air-results/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180607T150000
DTEND;TZID=America/Los_Angeles:20180607T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14530-1528383600-1528387200@www.cecs.uci.edu
SUMMARY:Modeling and Co-Design of Multi-domain Cyber-Physical Systems
DESCRIPTION:Name: Jiang Wan \nDate: Friday\, June 1 \nTime: 3:00 — 5:00 PM \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Mohammad Al Faruque\, Rainer Doemer \nAbstract: \nCyber-Physical Systems (CPS) are integration of computation and physical processes connected through networks. The high complexity of cross-domain engineering in combination with the pressure for system innovation\, higher quality\, time-to-market\, and budget constraints make it imperative for engineers to use integrated engineering methods and tools for CPS design. However\, existing computer-based engineering tools are mainly focused on a particular domain and therefore it is challenging to perform system-level analysis for CPS due to the difficulty of knowledge integration from different domains. This thesis studies the problem in the modeling of cross-domain CPS. Problems in the modeling of both functional and non-functional requirements during CPS design are explored and a functional model-based approach is proposed for high level CPS modeling. Moreover\, targeting the security requirement in CPS\, which is one of the key non-functional requirements in CPS\, physics-based models and solutions are proposed in this thesis. \n 
URL:https://www.cecs.uci.edu/event/modeling-and-co-design-of-multi-domain-cyber-physical-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180606T150000
DTEND;TZID=America/Los_Angeles:20180606T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14529-1528297200-1528300800@www.cecs.uci.edu
SUMMARY:Reliable and Energy Efficient Battery-Powered Cyber-Physical Systems
DESCRIPTION:Name: Korosh Vatanparvar\nDate: Wednesday\, May 30th \nTime: 3:00 — 5:00 PM \nLocation: Calit2 3008 \nCommittee: Professor Prof. Mohammad Al Faruque (Chair) \nAbstract: \nCyber-Physical Systems (CPS) were presented as a solution to multidisciplinary integration and control in embedded systems. They provide seamless interactions between cyber and physical domains\, enabling more intelligent and complicated control applications. However\, CPS face the challenges of reliability and energy efficiency since they mainly rely on batteries for power supply. \nWe investigate these issues with Electric Vehicles (EV) which are common battery-powered CPS. EV were introduced as a mean of transportation to address environmental problems like air and noise pollution. However\, their stringent design constraints\, especially on battery packs\, create challenges of limited driving range and battery lifetime for daily drivers and manufacturers. Design automation community has been addressing these by developing more efficient and dependable devices and control methodologies. Our contributions in this thesis will embrace: \n1) novel machine learning and physics-based modeling techniques to capture CPS dynamics more accurately; 2) unique optimization problem formulations to make optimal control decisions; and 3)intelligent control methodologies that leverage the modeling and interaction within CPS to achieve reliable and efficient operation. These contributions are applied to the systems in EV such as navigation system\, climate control\, and battery management system. Our objectives are to further extend the EV driving range and prolong the battery lifetime while maintaining similar driving experience and comfort for passengers. \n 
URL:https://www.cecs.uci.edu/event/reliable-and-energy-efficient-battery-powered-cyber-physical-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180517T150000
DTEND;TZID=America/Los_Angeles:20180517T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14526-1526569200-1526572800@www.cecs.uci.edu
SUMMARY:Reflective On-Chip Resource Management Policies for Energy-Efficient Heterogeneous Multiprocessors
DESCRIPTION:Name: Tiago Mück\nDate: May 16\, 2018 \nTime: 2:00pm \nLocation: Donald Bren Hall 2011 \nCommittee: Nikil Dutt (Chair)\, Alex Nicolau\, Tony Givargis \nAbstract: \nEffective exploitation of power-performance tradeoffs in heterogeneous many-core platforms (HMPs)\, requires intelligent on-chip resource management at different layers\, in particular at the operating system level. Operating systems need to continuously analyze the application behavior and find a proper answer for questions such as: What is the most power efficient core type to execute the application without violating its performance requirements? or Which option is more power-efficient for the current application: an out-of-order core at a lower frequency or an inorder core at a higher frequency?\nUnfortunately\, existing operating systems (e.g. Linux) do not offer mechanisms to properly address these questions and therefore are unable to fully exploit architectural heterogeneity for scalable energy-efficient execution of dynamic workloads.\nThis dissertation proposes a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software.\n\nThe general idea of reflection is to change your actions based on both external feedback and introspection (i.e.\, self-assessment).\n\n\nFrom a practical computer system perspective\, reflection means performing resource management actions considering both sensing information (e.g.\, readings from performance counters\, power sensors\, etc.) to assess the current system state\, as well as models to predict the behavior of the system before performing an action.\nIn this context\, this dissertation describes MARS\, a Middleware for Adaptive Reflective computer Systems. MARS consists of a framework and a set of models for creating reflective resource managers. MARS is implemented and evaluated on top a real Linux-based platform. Furthermore\, MARS also provides an offline simulation infrastructure for fast prototyping of policies and large-scale or long-term policy evaluation.\n\nExperimental evaluation shows that MARS’s models allow different policies for task mapping and dynamic voltage scaling to be seamlessly integrated\, resulting in up-to 1.8x energy efficiency improvements without performance degradation when compared to vanilla Linux.
URL:https://www.cecs.uci.edu/event/reflective-on-chip-resource-management-policies-for-energy-efficient-heterogeneous-multiprocessors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14525-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:SIMD Assisted Fault Detection and Fault Attack Mitigation
DESCRIPTION:Name: Zhi Chen\nDate: May 15\, 2018 \nTime: 2:30pm \nLocation: Donald Bren Hall 3011 \nCommittee: Professor Alex Nicolau (Chair)\, Alex Veidenbaum\, Nikil Dutt \nAbstract: \nModern processors continue to aggressively scale down the feature size and reduce voltage levels to run faster and be more energy efficient. However\, this trend also poses significant reliability concern as it makes transistors more susceptible to soft errors. Soft errors are transient. Although they don’t impair the computing systems permanently\, these errors can corrupt the output of a program or even crash the entire system. Hardware or software redundant techniques could be used to detect errors during the execution of a program. However\, hardware redundancy\, e.g. DMR (dual-modular redundancy) and TMR (triple-modular redundancy)\, leads to significant area overhead and very high energy cost. Software redundancy\, e.g. instruction duplication\, has lower performance and energy penalty and  virtually no hardware cost by sacrificing a small degree of error coverage. Yet commodity processors generally don’t require “five-nines” reliability as they are not mission-critical. Instead\, performance and energy consumption have more priority. This dissertation proposes a novel approach to instruction duplication\, which exploits the redundancy within SIMD instructions. The key idea is to pack the original data and its duplicate in the different lanes of the same vector register instead of executing two scalar instructions separately as these registers are underutilized on most applications. The proposed solution is implemented in the LLVM compiler as a stand-alone pass. Evaluation on a host of benchmarks reveal that proposed SIMD-based error detection technique causes much less performance\, code size\, and energy overheads.\n\nThis dissertation further extends the proposed approach as a countermeasure to protect cryptographic algorithms. These algorithms are widely adopted in modern processors and embedded systems to protect information. A number of popular cryptographic algorithms in the Libgcrypt library are protected using the SIMD-based instruction duplication technique. A large amount of errors are injected to these algorithms. The results show that almost all injected faults can be detected with reasonable performance and code size cost.\n 
URL:https://www.cecs.uci.edu/event/simd-assisted-fault-detection-and-fault-attack-mitigation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180503T150000
DTEND;TZID=America/Los_Angeles:20180503T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14517-1525359600-1525363200@www.cecs.uci.edu
SUMMARY:"Efficient Acceleration of Computation Using Associative In-memory Processing"
DESCRIPTION:Title: “Efficient Acceleration of Computation Using Associative In-memory Processing”\nSpeaker: Hasan Erdem Yantir\, University of California\, Irvine \nDate and Time: Monday\, May 14\, 2018 at 9:00AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi (Chair)\, Ahmed Eltawil\, Rainer Doemer \nAbstract: \nThe complexity of the computational problems is rising faster than the computational platforms’ capabilities. This forces researchers to find alternative paradigms and methods for efficient computing. One promising paradigm is accelerating compute-intensive kernels using in-memory computing accelerators since memory is the major bottleneck that limits the amount of parallelism and performance of a system and dominates energy consumption in computation. Leveraging the memory intensive nature of big data applications\, an in-memory-based computation system can be presented where logic can be replaced by memory structures\, virtually eliminating the need for memory load/store operations during computation. The massive parallelism enabled by such a paradigm results in highly scalable structures. \nThe present thesis is studied against this background. The objective is to conduct a broad perspective research on in-memory computing. For this purpose\, associative computing architectures (i.e.\, Associative Processors\, or AP) are built by both traditional (SRAM) and emerging (ReRAM) memory technologies together with their corresponding software frameworks. For ReRAM-based APs\, the reliability concerns coming with the emerging memories are resolved. Architectural innovations are developed to increase the energy efficiency. Furthermore\, approximate computing approach is introduced for APs to perform efficient/low-power approximate in-memory computing for the tasks which can tolerate some accuracy lost.  The works also propose a novel two-dimensional in-memory computing architecture to cope with the existing deficiencies of the traditional one-dimensional AP architectures.
URL:https://www.cecs.uci.edu/event/efficient-acceleration-of-computation-using-associative-in-memory-processing/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180411T150000
DTEND;TZID=America/Los_Angeles:20180411T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190729Z
UID:14516-1523458800-1523462400@www.cecs.uci.edu
SUMMARY:"A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models"
DESCRIPTION:Title: “A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models”\nSpeaker: Tim Schmidt\, University of California\, Irvine \nDate and Time: Friday\, April 20\, 2018 at 10:00AM-11:00PM \nLocation: Engineering Hall 3206 \nCommittee: Professor Rainer Doemer (Chair)\, Fadi Kurdahi\, Kwei-Jay Lin \nAbstract: \nThe design of embedded systems is a well-established research domain for many decades. However\, the constantly increasing complexity and requirements of state-of-the-art embed- ded systems pushes designers to new challenges while maintaining established design methodologies. Embedded system design uses the concept of Discrete Event Simulation (DES) to prototype and test the interaction of individual components. \nIn this dissertation\, we provide the Recoding Infrastructure for SystemC (RISC) compiler framework to perform static and hybrid analysis of IEEE SystemC models. On one hand\, RISC generates thread communication charts to visualize the communication between individual design components. The\nvisualization respects the underlying discrete event simulation semantics and illustrates the individual synchronization steps. On the other hand\, RISC translates a sequential model into a parallel model\nwhich effectively utilizes multi- and many-core host simulation platforms for faster simulation. This work extends the conflict analysis capabilities for libraries\, dynamic memory allocation\, channel instance awareness\, and references. Additionally\, the traditional thread level parallelism is extended with data level parallelism for even faster simulation.
URL:https://www.cecs.uci.edu/event/a-compiler-infrastructure-for-static-and-hybrid-analysis-of-discrete-event-system-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171114T150000
DTEND;TZID=America/Los_Angeles:20171114T160000
DTSTAMP:20231011T190709Z
CREATED:20231011T190702Z
LAST-MODIFIED:20231011T190709Z
UID:14501-1510671600-1510675200@www.cecs.uci.edu
SUMMARY:"Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems"
DESCRIPTION:Title: “Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems”\nSpeaker: Majid Namaki Shoushtari\, University of California\, Irvine \nDate and Time: Tuesday\, November 7\, 2017 at 11:00AM-12:00PM \nLocation: Donald Bren Hall 2011 \nAbstract:\nThe growing computing demands of emerging application domains such as Recognition/Mining/Synthesis (RMS)\, visual computing\, wearable devices and the Internet of Things (IoT) has driven the move towards manycore architectures to better manage tradeoffs among performance\, energy efficiency\, and reliability.\nThe memory hierarchy of manycore architectures has a major impact on their overall performance\, energy efficiency and reliability. We identify three major problems that make traditional memory hierarchies unattractive for manycore architectures and their data-intensive workloads: (1) they are power hungry and not a good fit for manycores in face of dark silicon\, (2) they are not adaptable to the variable workload’s requirements and memory behavior\, and (3) they are not scalable due to coherence overheads. \nThis thesis argues that many of these inefficiencies are the result of software-agnostic hardware-managed memory hierarchies. Application semantics and behavior captured in software can be exploited to more efficiently manage the memory hierarchy. This thesis exploits some of this information and proposes a number of techniques to mitigate the aforementioned inefficiencies in two broad contexts: (1) explicit management of hybrid cache-SPM memory hierarchy\, and (2) exploiting approximate computing to improve the energy efficiency of the memory hierarchy.\nWe first present the required hardware and software support for a software-assisted memory hierarchy that is composed of distributed memories which can be partitioned between caches and SPMs at runtime. We discuss our SPM APIs\, the protocol needed for data movements\, and our approach for explicit management of shared data.\nNext\, we augment caches and SPMs in this hierarchy with approximation support in order to improve the energy efficiency of the memory subsystem when running approximate programs.\nFinally\, we discuss a quality-configurable memory approximation strategy using formal control theory that adjusts the level of approximation at runtime depending on the desired quality for the program’s output. \n 
URL:https://www.cecs.uci.edu/event/software-assists-to-on-chip-memory-hierarchy-of-manycore-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170531T150000
DTEND;TZID=America/Los_Angeles:20170531T160000
DTSTAMP:20231011T190636Z
CREATED:20231011T190636Z
LAST-MODIFIED:20231011T190636Z
UID:14486-1496242800-1496246400@www.cecs.uci.edu
SUMMARY:Quoc-Viet Dang PhD Defense
DESCRIPTION:Name: Quoc-Viet Dang\nDate: May 30\, 2017 \nTime: 02:00 P.M \nLocation: Engineering Hall 3206 \nCommittee: Professor Daniel Gajski (Chair)\, Fadi Kurdahi\, Rainer Doemer \nAbstract: \nPublic education is on the brink of a potential crisis attempting to significantly increase student enrollment while maintaining quality of education. Online courses have been proposed and debated among members of the UC regents\, numerous college administrators\, faculty\, and students. On one hand\, online education can reduce overhead while enrolling more students. Directly translating the classroom lectures and materials to an online environment does not necessarily produce equivalent student performance and satisfaction from the course compared to an in-class environment. Since there is no universal standard for online education\, erratic and inconsistent results have been achieved in terms of student performance and costs to students as well as administration. A hybrid scalable teaching and learning methodology is required by both educators and students to achieve the greatest advantages of using today’s technology and apply it toward improving student performance and participation. \nThis dissertation presents a methodology and system to provide a more individualized and responsive learning environment for students in large hybrid and online university courses while keeping overall costs and time commitment down as well as improve overall student performance. The Universal Personal Advisor\, the implemented learning design tool of this research\, is developed based on multi-disciplinary metrics and studies from the fields of Psychology\, Education\, and Engineering. A primary limiting resource for both students and instructors is time. By automating some basic key interactions that may occur between students and instructors\, hours of each individual’s time can be saved\, maximizing the quality of the available in-person interactions to occur during a course while allowing for a more scalable sized classroom environment.
URL:https://www.cecs.uci.edu/event/quoc-viet-dang-phd-defense/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170526T150000
DTEND;TZID=America/Los_Angeles:20170526T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190642Z
UID:14485-1495810800-1495814400@www.cecs.uci.edu
SUMMARY:Robust Data Hiding in Multimedia for Authentication and Ownership Protection
DESCRIPTION:Name: Farhan A. Alenizi\nDate: May 26th\, 2017 \nTime: 10:00 AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi \nAbstract: \nEstablishing robust and blind data hiding techniques in multimedia is very important for authentication\, ownership protection and security. The multimedia being used may include images\, videos and 3D mesh objects. A hybrid pyramid Discrete-Wavelet-Transform (DWT) Singular-Value-Decomposition (SVD) data hiding scheme for video authentication and ownership protection is proposed. The data being hidden will be in the shape of a main  color logo image watermark and another secondary Black and White (B&W) logo image.   The color watermark will be decomposed to Bit-Slices.   A pyramid transform is performed on the Y-frames of a video stream resulting in error images;  then\, a Discrete Wavelet Transform (DWT) process is implemented using orthonormal filter banks on these  error images\, and the Bit-Slices watermarks are inserted in one or more of the resulting subbands in a way that is fully controlled by the owner; then\, the watermarked video is reconstructed. SVD will be performed on the color watermark Bit-Slices. A secondary B&W watermark will be inserted in the main color watermark using another SVD process.     The reconstruction was perfect without attacks\, while the average Bit-Error-Rates (BER’s) achieved under attacks are in the limits of  2% for the color watermark and 5% for the secondary watermark; meanwhile\,  the mean Peak Signal-to-Noise Ratio (PSNR) is 57 dB. Furthermore\, a selective denoising filter to eliminate the noise in video frames is proposed; and the performance with data hiding is evaluated. \n  \nMoreover\, a 3D mesh blind  optimized watermarking   technique is proposed in this research. The technique relies on  the displacement process of  the vertices locations depending on the modification of the  variances of the vertices’s norms. Statistical analysis were performed to establish the proper distributions that best fit each mesh\, and hence establishing the bins sizes.   Experimental results showed that the approach is robust in terms of both the perceptual  and the quantitative  qualities. \n  \nIn conclusion\,  the degree of robustness and security  of the  proposed techniques are shown. Also the schemes that can be adopted to further enhance the performance\,  and the future work that can be done in the field are introduced. \n 
URL:https://www.cecs.uci.edu/event/robust-data-hiding-in-multimedia-for-authentication-and-ownership-protection/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170515T150000
DTEND;TZID=America/Los_Angeles:20170515T160000
DTSTAMP:20231011T190638Z
CREATED:20231011T190638Z
LAST-MODIFIED:20231011T190638Z
UID:14490-1494860400-1494864000@www.cecs.uci.edu
SUMMARY:Millimeter-wave and Sub-THz Signal Generation and Detection in Silicon Technologies
DESCRIPTION:Name: Peyman Nazari\nDate: May 15\, 2017 \nTime: 10:00 AM \nCommittee: Prof. Payam Heydari (Chair). Prof. Michael Green\, Prof. Ahmed Eltawil \nAbstract:  \nMM-wave/sub-Terahertz (THz) signal generation\, radiation\, and detection have become increasingly attractive due to its fast-growing applications in spectroscopy\, radar\, biomedical and security imaging as well as high-speed wireless communication.\n\n\nSilicon technology\, in one hand\, offering high-density signal processing capabilities due to aggressive scaling of its feature size\, and on the other hand\, allowing integration of mm-wave/THz antenna elements owing to their shrunk footprint at these bands\, is well-suited for implementation of fully-integrated multi-antenna mm-wave/THz wireless System-on-Chips (SoC’s).\n\n\nPerformance of such system is dominantly governed by the quality and efficiency of signal generation\, transmission\, and detection. Passive and active components as means of realizing these functionalities must be optimized for operation at these frequency ranges. However\, excessive loss of on-chip passive components and limited gain and output power of transistors at such high frequencies demand novel passive and active structures. Furthermore\, high level of integration implies that the co-design of front-end components leads to a better end-to-end performance\, thus a holistic design methodology must be employed. Radiation characteristics of the wireless signal must also be engineered to improve its transmission quality. For example\, circularly polarized radiation is found to be a viable choice for many imaging and communication applications by exhibiting excellent robustness against de-polarization effects.\n\n\nIn this dissertation\, silicon realization of on-chip waveguides\, as low loss mediums for high-frequency wave propagation\, is explored and implementations of low-loss cavity-backed passives are discussed. Furthermore\, a silicon-integrated IMPATT diode\, together with its fabrication and modeling is introduced as a solution for obtaining active behavior beyond fmax of transistors. Next\, a high-power/efficiency mm-wave circularly-polarized cavity-backed radiator\, employing a multi-port multi-function passive network as a resonator\, power combiner\, and antenna\, is introduced. Necessary conditions for robust operation of such multi-port oscillators/radiators are also derived. Fabricated in a 0.13µm SiGe BiCMOS process\, the prototype chip achieves 14.2dBm EIRP\, -99.3dBc/Hz phase noise at 1MHz offset\, and 5.2% DC-to-EIRP conversion efficiency which is the highest reported value among silicon-based radiators not using silicon lens or substrate processing.\n\n\nFinally\, a 210GHz low noise amplifier (LNA) is presented to address the detection challenges. This LNA\, achieves 18dB of gain\, with less than 12dB noise-figure and 3dB bandwidth of more than 15GHz\, thereby showing best performance metrics among prior work. This is achieved by incorporating circuit and EM techniques enabling simultaneous optimization of stable gain-\, noise- and bandwidth-performance parameters at this frequency range.
URL:https://www.cecs.uci.edu/event/millimeter-wave-and-sub-thz-signal-generation-and-detection-in-silicon-technologies/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170307T150000
DTEND;TZID=America/Los_Angeles:20170307T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14482-1488898800-1488902400@www.cecs.uci.edu
SUMMARY:Optimizing Many-Threads-to-Many-Cores Mapping in Parallel Electronic System Level Simulation
DESCRIPTION:Name: Guantao Liu\nDate: March 2\, 2017 \nTime: 4:00 PM \nLocation: Engineering Hall 3206 \nCommittee: Rainer Doemer (Chair)\, Kwei-Jay Lin\, Mohammad Al Faruque \nAbstract: \nIn hardware/software co-design\, Discrete Event Simulation (DES) has been in use for decades to verify and validate the functionality of Electronic System Level (ESL) models. Since the parallel computing platforms are readily available today\, many Parallel Discrete Event Simulation (PDES) approaches are proposed to improve the simulation performance. However\, as the thread parallelism increases in ESL designs and core count multiplies on multi-core and many-core platforms\, thread-to-core mapping becomes critical in PDES. \nIn this dissertation\, we propose a computation- and communication-aware approach to optimize thread mapping for parallel ESL simulation\, with the aims of load balancing and communication minimization. As we identify that the order of dispatching parallel threads has a significant influence on the total simulation time\, and Longest Job First (LJF) shows better performance than the Linux default thread dispatch policy\, we first propose a segment- aware LJF scheduler for PDES. Our segment-aware scheduler can accurately predict the run time of the thread segments ahead\, and thus make better dispatching decisions. Next\, we define the concept of core distance for multi-core and many-core architectures\, which quantifies core-to-core communication latency and characterizes processor hierarchies. For many-core architectures using directory-based cache coherence protocols\, we observe that core-to-core transfers are not always significantly faster than main memory accesses\, and the core-to-core communication latency depends not only on the physical placement on the chip\, but also on the location of the distributed cache tag directory. Thus\, using a memory ping-pong benchmark\, we quantify the core distance on a ring-network many-core platform and propose an algorithm to optimize thread-to-core mapping in order to minimize on-chip communication overhead. Altogether\, based on a static analysis of communication patterns and core distance and a dynamic profiling of computation load\, our proposed framework utilizes a heuristic graph partitioning algorithm and automatically generates an optimized thread mapping\, which minimizes inter-chip communication overhead. In our systematic evaluation\, our approach consistently shows a significant performance gain on top of the order-of-magnitude speedup of PDES. \nThe contributions of this dissertation include a segment-aware multi-core scheduler\, core distance profiling\, a communication-aware thread mapping framework\, together with an open-source software package for Out-of-Order PDES.
URL:https://www.cecs.uci.edu/event/optimizing-many-threads-to-many-cores-mapping-in-parallel-electronic-system-level-simulation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170221T150000
DTEND;TZID=America/Los_Angeles:20170221T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14481-1487689200-1487692800@www.cecs.uci.edu
SUMMARY:Low Power Reliable Design using Pulsed Latch Circuits
DESCRIPTION:Name: Wael Mahmoud Elsharkasy \nDate: February 15\, 2017 \nTime: 11:00 AM \nLocation: Engineering Hall 3206 \nCommittee: Prof. Fadi J. Kurdahi\, Prof. Ahmed Eltawil\, Rainer Doemer \nAbstract: \nSystem-on-Chip (SoC) faced lots of challenges over the past decade. With nowadays applications centered around Internet-of-Everything (IoE)\, these challenges are expected to be more critical. Among these challenges are the reduction of power consumption for better energy efficiency\, the overcoming of different sources of variations to ensure reliable operation and the reduction of design area to reduce the cost and increase the integration. As a result\, chip designers find themselves facing lots of problems\, trying to build reliable systems that integrate complex level of functionality\, on a minimum die size and with a limited power budgets. Among different circuit components in every chip\, memory components are of great concern. They consume the majority of the chip area and power\, in addition to affecting the entire chip performance and reliability. These include large memory arrays\, caches\, register files and different sequential elements in the logic paths. Sequential elements play an important and critical role in modern synchronous CMOS circuits. Indeed\, they can represent up to 50% of the standard cells used in a chip. In addition\, the power consumption of the clock tree\, including these elements can be more than half of the total chip power. In addition\, they come in the second place after memory to be affected by different sources of variation. Hence\, efficient implementation of these elements is of great importance for the design of energy efficient and reliable integrated circuits. Pulsed latches have been proposed as efficient replacement of flip-flops in the implementation of sequential element. They can achieve higher performance when compared to traditional flip-flop\, and can be designed to be smaller in area and more power efficient. However\, the operation of pulsed latch is more sensitive to process\, voltage and temperature (PVT) variations. In this thesis\, we are proposing a methodology to study the reliability of pulsed latches and we have used it to evaluate the effect of PVT variations on their behavior. In addition\, novel approaches to enhance the reliability of pulsed latches without significant degradation in performance\, area or power are presented. Also\, since sequential elements can be used to build small size register files\, pulsed latch implementation of register files are discussed and compared to other traditional implementations\, including SRAM and flip-flops. In addition\, since multiport register files are very beneficial for quite few applications\, novel implementations of multiport register files are also presented. The proposed implementation is proved to highly reduce the significant overhead in area\, power and latency associated with the traditional way of designing multiport register files.
URL:https://www.cecs.uci.edu/event/low-power-reliable-design-using-pulsed-latch-circuits/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170131T150000
DTEND;TZID=America/Los_Angeles:20170131T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14479-1485874800-1485878400@www.cecs.uci.edu
SUMMARY:Runtime Memory Management in Many-core Systems
DESCRIPTION:Name: Hossein Tajik\nDate: November 15\, 2016 \nTime: 3:00PM – 4:00PM \nLocation: DBH 3011 Conference Room \nCommittee: Nikil Dutt (Chair)\, Tony Givargis\, Alex Nicolau \nAbstract: \nWith the increasing number of cores on a chip\, we are moving towards an era where many-core platforms will soon be ubiquitous. Efficient use of tens to hundreds of cores on a chip and their memory resources comes with unique challenges. \nIn this dissertation\, we propose SPMPool: a scalable platform for sharing Software Programmable Memories (SPMs). The SPMPool approach exploits underutilized memory resources by dynamically sharing SPM resources between applications running on different cores and adapts to the overall memory requirements of multiple applications that are concurrently executing on the many-core platform. We propose both central and distributed management schemes for SPMPool and study the efficiency of auction-based mechanisms in solving the memory mapping problem. We also propose offline and online memory phase detection methods in order to increase the adaptivity of memory management to temporal changes in memory requirements of a single application. The runtime memory management schemes proposed in this dissertation enable better performance and power for many-core systems.
URL:https://www.cecs.uci.edu/event/runtime-memory-management-in-many-core-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170130T150000
DTEND;TZID=America/Los_Angeles:20170130T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14492-1485788400-1485792000@www.cecs.uci.edu
SUMMARY:On Optimizing the Performance of Interference-Limited Wireless Systems
DESCRIPTION:Name: Rana A. Abdelaal\nDate: January 30\, 2017 \nTime: 1:00 PM \nLocation: Engineering Hall 3106 \nCommittee: Professor Ahmed Eltawil \nAbstract: \nMulti Input Multi Output (MIMO) technology has seen prolific use to achieve higher data rates and an improved communication experience for cellular systems. However\, one of the challenging problems in MIMO systems is interference. Interference limits the system performance in terms of rate and reliability. In this thesis\, we analyze methods that provide high performance over interference-limited wireless networks such as Long Term Evolution (LTE) and WiFi. In this thesis\, we tackle different sources of interference. One of the interference sources is the neighboring interference\, we propose methods that include an optimized solution that models the interference as correlated noise\, and uses its statistical information to jointly optimize the base station precoding and user receiver design of LTE systems. We study the benefits of exploiting interference in terms of both probability of error and signal-to-noise ratio (SNR). In addition\, we compare the proposed method with the conventional beamforming and maximum ratio combining (MRC). One of the key challenges to enable high data rates in the downlink of LTE is the precoding and receiver design. We focus primarily on the UE and the base station (BS) processing\, particularly on estimating and using the interference resulting from neighboring stations. In this thesis\, we propose a receiver design that performs well in the presence of interference. Furthermore\, we present a precoding scheme that the BS can use to maximize the signal-to-interference plus noise-ratio (SINR). An interference free scenario is used as a benchmark to evaluate the proposed system performance. In this thesis\, we optimize the performance of LTE by tackling practical considerations that affects the system performance. We present a suboptimal practical way of estimating the interference and utilizing this information on the processing techniques used at both the UE and the eNodeB sides. We focus on managing both MU-MIMO interference and other cell interference. The proposed study improves system performance even under non-perfect channel knowledge\, enabling the throughput gains promised by MU-MIMO. \nOther types of interference exist in In-band full-duplex (IBFD) communication systems. IBFD is very promising in enhancing wireless LANs\, where full-duplex access points (APs) can support simultaneous uplink (UL) and downlink (DL) flows over the same frequency channel. One of the key challenges limiting IBFD benefits is interference. In this thesis\, we also propose a scheduling technique to manage interference in wireless LANs with full-duplex capability. We focus primarily on scheduling UL and DL stations (STAs) that can be efficiently served simultaneously. \nIt is very important to apply system knowledge to reduce power and/or improve performance. Thus\, we also aim at exploring energy and power management techniques for practical wireless communication systems. An important topic for practical communication systems is handling the interference due to the power amplifier nonlinearities. Managing this type of interference is of very high importance\, especially in Orthogonal Frequency-Division Multiple Access (OFDMA) based communication systems. Although\, OFDMA is the modulation of choice due to its robustness to time-dispersive radio channels\, low-complexity receivers\, and simple combining of \nsignals from multiple transmitters in broadcast networks. The transmitter design for OFDMA is more costly\, as the Peak-to-Average Power Ratio (PAPR) of an OFDMA signal is relatively high\, resulting in the need for highly linear RF power amplifiers (PA). This problem becomes more compounded when a large number of PAs is required\, as in Massive MIMO for example. In this thesis\, we discuss the impact of PAs on cellular systems. We show the constraints that PAs introduce\, and we take these constraints into consideration while searching for the optimum set of transmitter and receiver filters. Moreover\, we highlight how Massive MIMO cellular networks can relax PAs constraints resulting in low cost PAs\, while maintaining high performance. The performance is evaluated by showing the probability of error curves and signal-to-noise-ratio curves for different transmit powers and different number of transmit antennas. Another promising topic for efficient practical communication systems is Associative processors (APs). AP is a good candidate for in-memory computation\, however it has been deemed too costly and energy hungry in the past. The advent of ultra-dense resistive memories is changing this paradigm\, allowing for efficient in-memory associative processors. However\, with high levels of integration\, issues related to power density become the bottleneck. In this thesis\, we show the potential use of the approximate computing in wireless communication systems\, specifically\, we present Fast Fourier Transform (FFT) implemented by associative processor. Results confirm that approximate computing for in-memory associative processors is a viable approach to reduce power consumption while maintaining good performance. A promising approach to save energy is through reducing the bit width\, however reducing the bit width introduces errors that may affect the performance. In this thesis\, our goal is to adjust the bit width based on the channel SNR\, aiming at achieving good performance at reduced energy consumption. The mathematical approach that analytically describes the system performance under the reduced bit width noise is presented. Based on this model\, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves performance goals at reduced energy consumption. Simulation results show that the proposed algorithms can achieve up to 45% energy savings as compared to wireless communication systems with conventional FFT. \n 
URL:https://www.cecs.uci.edu/event/on-optimizing-the-performance-of-interference-limited-wireless-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161206T150000
DTEND;TZID=America/Los_Angeles:20161206T160000
DTSTAMP:20231011T190622Z
CREATED:20231011T190622Z
LAST-MODIFIED:20231011T190622Z
UID:14476-1481036400-1481040000@www.cecs.uci.edu
SUMMARY:Scalable Runtime support for Edge-To-Cloud integration of Distributed Sensing Systems
DESCRIPTION:Name: Brett Chien\nDate: November 29\, 2016 \nTime: 10:00AM \nLocation: EH 2210 \nCommittee: Pai H. Chou (Chair) \nAbstract:  \nWhile Internet-Of-Things (IoT) has drawn more attention to researchers and the public\, to build a complete system from the edge sensing units to the cloud services requires massive amount of efforts. Researchers with strong interests in collected information are often lost in various technologies\, including distributed sensing embedded systems\, bridge devices between Internet and local network\, and data backend services. \nThis work takes a cross-system\, script-based\, and semantic-enhanced approach to address the problem of lacking suitable runtime supports. We proposed a threaded code runtime support for edge sensing systems\, a script based wrapper on Physical-to-Cyber bridges\, and scalable middleware into the backend services. \nWith proposed runtime supports\, we are able to apply distributed sensing systems into real world applications quickly and explorer insights from collected information. As a result\, a building structure monitoring system is installed and allow civil researchers to develop algorithms to prevent disaster events. Body area sensing systems such as ECG monitoring\, CO2 detection\, and body movement are developed. This enables baby screening and detect potential heart problems. The results have shown that with proposed runtime supports applications can be realized quickly and scalable.
URL:https://www.cecs.uci.edu/event/scalable-runtime-support-for-edge-to-cloud-integration-of-distributed-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161114T150000
DTEND;TZID=America/Los_Angeles:20161114T160000
DTSTAMP:20231011T190617Z
CREATED:20231011T190617Z
LAST-MODIFIED:20231011T190617Z
UID:14475-1479135600-1479139200@www.cecs.uci.edu
SUMMARY:Resource Aggregation for Collaborative Projected Video from Multiple Mobile Devices
DESCRIPTION:Name: Hung Nguyen\nDate: November 17\, 2016 \nTime: 1:30 P.M. \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Aditi Majumder (Co-Chair) \nAbstract:  \nWe explore and develop an embedded real time system and associated algorithms that enable an aggregation of limited resource\, low-quality\, projection-enabled mobile devices to collaboratively produce a higher quality video stream for a superior viewing experience. Such a resource aggregation across multiple projector enabled devices can lead to a per unit resource savings while moving the cost to the aggregate. \nThe pico-projectors that are embedded in mobile devices such as cell phones have a much lower resolution and brightness than standard projectors. Tiling (putting the projection area of multiple projectors in a rectangular array overlapping them slightly around the boundary) and superimposing (putting the projection area of multiple projectors right on top of each other) multiples of such projectors\, registered via automated registration through the cameras residing within those mobile devices\, result in different ways of aggregating resources across these multiple devices. Evaluation of our proof-of-concept system shows significant improvement for each mobile device in two primary factors of bandwidth usage and power consumption when using a collaborative federation of projection-embedded mobile devices. \nThe portable\, low-power\, light weight\, small size pico-projectors are key components of projection-enabled mobile devices for the future. Due to the reduction of weight and dimension and the portability nature of the projector-enabled mobile devices\, the calibrated integrated systems are prone to physical un-stabilizing of the projected image during the presentation. Thus the auto re-calibration and projected video stabilization features during the presentation time becomes essential requirements to enhance user experience. The design\, algorithm\, and implementation methods for these features will be presented in the second part of the dissertation.
URL:https://www.cecs.uci.edu/event/resource-aggregation-for-collaborative-projected-video-from-multiple-mobile-devices/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161004T150000
DTEND;TZID=America/Los_Angeles:20161004T160000
DTSTAMP:20231011T190615Z
CREATED:20231011T190615Z
LAST-MODIFIED:20231011T190615Z
UID:14469-1475593200-1475596800@www.cecs.uci.edu
SUMMARY:Specification and Runtime Verification of Distributed Multiprocessor Systems: Languages\, Tools and Architectures
DESCRIPTION:Name: Ahmed Nassar\nDate: September 2\, 2016 \nTime: 12:00 P.M. \nLocation: EH 3403 \nCommittee: Fadi Kurdahi (Chair)\, Rainer Doemer\, Ahmed Eltawil \nAbstract: Post-Deployment runtime verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification and testing methods. This thesis is an attempt to tackle three major barriers that need to be surmounted before RV technologies become in widespread use:\nBarrier-1: Lack of an expressive\, yet efficiently monitorable\, specification language. Distributed software behavior is projected onto an observation interface consisting of data-carrying (or parameterized) events\, such as Linux system calls including argument values\, and self-replicating deterministic finite automata (SR-DFAs) are introduced for RV purposes as well as anomaly-based intrusion detection in embedded and general-purpose software systems based on these parametric traces.\nBarrier-2: The substantial performance and power overhead of pure software RV frameworks. NUVA\, which stands for nonuniform verification architecture\, a distributed automata-based RV architecture for software specifications in the form of SR-DFAs. NUVA has been implemented over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor and can be deployed on the FPGA fabric that will reside on all next-generation processor chips. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes.\nBarrier-3: Formal specifications are hard to formulate and maintain for evolving complex embedded and general-purpose software systems. Therefore\, specification mining has long ago been envisioned to play a key role in software verification\, modification and documentation. However\, in order to scale beyond simple\, library/API-level properties having short temporal spans\, specification mining tools need to support more expressive specification languages that can capture complex\, application-level properties. This thesis introduces a bio-inspired complete specification mining methodology for SR-DFAs using an iterative and interactive mining tool\, called ParaMiner. ParaMiner relies on novel mining algorithms invoking multiple-sequence alignment (MSA) techniques to enable learning specifications from temporal slices of software behavior while overcoming the initial-state uncertainty problem.\nSR-DFAs and ParaMiner have been leveraged in a new specification-based intrusion detection (ID) framework that protects distributed\, reactive computing systems against cyberattacks having very sparse signatures\, arbitrarily long time spans and wide attack fronts. Such attacks lie outside the scope of conventional anomaly-based ID methods which typically work with short event windows and ignore manipulated data objects\, such as files and sockets. We demonstrate the effectiveness of the constructed SR-DFAs at classifying as well as resolving subtle behaviors typical of cyberattacks with varying evasion parameter values.
URL:https://www.cecs.uci.edu/event/specification-and-runtime-verification-of-distributed-multiprocessor-systems-languages-tools-and-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160818T150000
DTEND;TZID=America/Los_Angeles:20160818T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190553Z
LAST-MODIFIED:20231011T190555Z
UID:14449-1471532400-1471536000@www.cecs.uci.edu
SUMMARY:PhD Defense:
DESCRIPTION:Name:  Aras Pirbadian\nDate: August 29\, 2016 \nTime: 3:30pm \nLocation:  EH 3403 \nCommittee: Ahmed Eltawil (Chair)\, Fadi Kurdahi\, Rainer Doemer \nWith the continued scaling of chip manufacturing technologies\, the significance of process variation in performance of the systems is increasing. Specifically\, process variation results in growing voltage and frequency overhead margins required to ensure error free operation of circuits. However\, the traditional practice of overdesigning the systems to cover process variation is no longer an efficient design methodology in an age with high demands for processing power and limited energy supplies. In this dissertation\, a novel analytical model is proposed to predict the required margin accurately in the early stages of design space exploration. The model can be used to optimize the system overhead in error free calculations or to release the bound by full correctness in error tolerant parts of systems and optimize the energy vs. performance trade-off. Additionally\, this model also considers the statistics of the inputs of the circuit as compared to other existing efforts enabling it to achieve close predictions of full circuit simulation results in a short time. This model is finally used in an adaptive carry select/ripple carry adder configuration to demonstrate the potential achievable power savings. \nGrowing variation in newer technology nodes is not always a negative side effect. The increased inherent randomness in the process manufacturing technology can be utilized to develop unique physically unclonable functions (PUFs). These functions are irreproducible hardware-based authenticating systems\, which do not require memory-based storage. A low overhead delay-based PUF using the variation of the silicon manufacturing is also proposed in the second part of this work. The proposed PUF uses a simple and efficient structure to convert the randomness of the manufacturing process into random responses to fixed challenges in identically designed circuits.
URL:https://www.cecs.uci.edu/event/phd-defense/
CATEGORIES:PhD Defenses
END:VEVENT
END:VCALENDAR