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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240809T143000
DTEND;TZID=America/Los_Angeles:20240809T153000
DTSTAMP:20240814T140023Z
CREATED:20240814T140023Z
LAST-MODIFIED:20240814T140023Z
UID:16354-1723213800-1723217400@www.cecs.uci.edu
SUMMARY:Hardware/Software Co-design Methodologies for Efficient AI Systems and Applications
DESCRIPTION:Name: Mohanad Odema \nChair: Prof. Mohammad Abdullah Al Faruque \nDate: August 9\, 2024 \nTime:  2:30 PM \nLocation: EH 2430 \nCommittee: Prof. Marco Levorato\, Prof. Hyouk Jun Kwon \nTitle: Hardware/Software Co-design Methodologies for Efficient AI Systems and Applications \nAbstract: The landscape of AI research is dominated by the search for powerful deep learning models and architectures that enable fascinating applications from the edge to the cloud. Indeed\, we have witnessed the emergence of efficient\, on-device deep learning models that facilitate smart edge applications (autonomous vehicles\, AR/VR systems)\, and the emergence of billion parameter foundation/LLM models that excel at tasks thought achievable only through human-level understanding. On the other hand\, the calls for more advanced hardware and systems continue to grow considering the scale at which deep learning model workloads evolve\, and to facilitate sustainable\, efficient model operation across the various application contexts. \nThis suggests a natural way to design deep learning models and their systems: viz\, through hardware/software co-design methodologies\, capturing the interplay and mutual dependencies across various HW/SW layers of the computing stack to guide different design choices. From the algorithmic side\, an awareness of the target platform’s compute capabilities and resources guides the deep learning model architectural and optimization choices (e.g.\, compression) towards maximizing performance efficiency on the target hardware at deployment time. From the hardware side\, understanding the deep learning workloads and computing kernels can shape future architectures of AI hardware that improves on efficiency from the lower levels (as seen through customized accelerators trend). \nAs hardware and software continue to undergo continuous innovation\, this dissertation aims to investigate relevant emergent technologies and challenges at this unified research frontier to guide the design of future AI systems and models. The dissertation focuses on characterizing nascent design spaces\, exploring various optimization opportunities\, and developing new methodologies to maximize the impact of such innovations. In brief\, this dissertation goes over the following topics: \n– Understanding the benefits of dynamic neural networks for efficient inference\, and how to optimize their design for target platform deployment \n– Understanding how multi-model workloads can be scheduled and co-located on multi-chip AI Accelerator modules based on 2.5D chiplets technology while accounting for workloads’ diversity\, affinities\, and memory access patterns \n– Exploring new methodologies to maximize the impact of split computing inference in edge-cloud architectures\, and elevate resource efficiency of edge devices \nShort Bio: Mohanad received a B.Sc degree in Electronics and Communications and a M.Sc degree in Computer Engineering from Ain Shams University\, Egypt. He is a PhD Candidate in Computer Engineering at UCI. He was an intern at MediaTek with the AI Architecture and Algorithm team. His research interests are focused on HW/SW co-design solutions for efficient AI\, bridging model- and system-level optimizations to enhance performance for core industry AI workloads and applications from the edge to the cloud.
URL:https://www.cecs.uci.edu/event/hardware-software-co-design-methodologies-for-efficient-ai-systems-and-applications/
LOCATION:EH 2430\, Engineering Hall\, University of California\, Irvine\, Irvine\, CA\, 92697\, United States
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250224T100000
DTEND;TZID=America/Los_Angeles:20250224T110000
DTSTAMP:20250224T172059Z
CREATED:20250224T172059Z
LAST-MODIFIED:20250224T172059Z
UID:16404-1740391200-1740394800@www.cecs.uci.edu
SUMMARY:Navigating Cybersecurity in the AI Era: Strategies and Defense Mechanisms
DESCRIPTION:Name: Jiacen Xu \nChair: Prof. Zhou Li \nDate: February 24\, 2025 \nTime:  10:00 AM \nLocation: Zoom \nCommittee: Prof. Mohammad Al Faruque\, Prof. Yanning Shen \nTitle: Navigating Cybersecurity in the AI Era: Strategies and Defense Mechanisms \nAbstract: The rise of AI has dramatically reshaped the cybersecurity landscape\, introducing both advanced cyber threats and innovative defense mechanisms. My research delves into the evolving nature of cyber attacks and AI-driven defenses\, with a particular focus on how AI both exacerbates and addresses cybersecurity risks. \nI examine the progression of AI-powered cyber-attacks\, highlighting how these technologies enable more precise\, autonomous\, and scalable breaches across a range of digital infrastructures\, including enterprise network systems and IoT systems like autonomous vehicles. The research explores AI-driven attack vectors such as automated malicious command generation and adversarial machine learning techniques targeting autonomous systems. \nIn response\, my research evaluates AI-powered defense strategies\, such as graph neural networks for threat detection and AI-augmented forensic analyses\, using datasets from DARPA DC and Los Alamos National Lab. These defense mechanisms are assessed for their ability to detect and mitigate threats. \nThe goal of my research is to provide a comprehensive understanding of the dual role of AI in cybersecurity and propose strategic measures to strengthen security practices in response to the rapid pace of technological advancement. \nShort Bio: Jiacen Xu is a Ph.D. candidate in Electrical Engineering and Computer Science at the University of California\, Irvine\, under the supervision of Professor Zhou Li. He holds a B.Sc. and M.Sc. in Information Security and Cyberspace Security from Shanghai Jiao Tong University. His research focuses on Artifact Intelligence for cybersecurity applications such as cyber attack automation and detection. During his Ph.D.\, he interned at Microsoft Research and IBM Research.
URL:https://www.cecs.uci.edu/event/navigating-cybersecurity-in-the-ai-era-strategies-and-defense-mechanisms/
LOCATION:Zoom
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250311T100000
DTEND;TZID=America/Los_Angeles:20250311T110000
DTSTAMP:20250310T202338Z
CREATED:20250310T202256Z
LAST-MODIFIED:20250310T202338Z
UID:16415-1741687200-1741690800@www.cecs.uci.edu
SUMMARY:Modeling and Evaluation of a Cache-less Grid of Processing Cells
DESCRIPTION:Name: Vivek Govindasamy \nChair: Prof. Rainer Doemer \nDate: March 11\, 2025 \nTime: 10:00 AM \nLocation: EH 3206 (CECS Conference Room) \nCommittee: Prof. Mohammad Al Faruque\, Prof. Ian Harris \nTitle: Modeling and Evaluation of a Cache-less Grid of Processing Cells \nAbstract: Modern processors experience memory contention when the speed of their computational units exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory wall and is a great challenge in computer engineering. The reason for this phenomenon is the unequal growth rate in memory access speeds compared to processor clock rates. In order to mitigate the memory bottleneck in classic computer architectures\, a scalable parallel computing platform called the Grid of Processing Cells (GPC) has been proposed. To evaluate its effectiveness\, we model the GPC in this work at the instruction-level and functional-level using SystemC TLM-2.0\, with a focus on memory contention. In an advanced model\, individual GPC cells can be switched as needed between the two abstraction levels. We then show that our mixed-level system model enables fast and accurate simulations. We test multiple streaming applications on the GPC\, analyze software-based optimization methods and their effects on the GPC\, at both abstraction levels. The performance is then compared against the traditional shared memory processor (SMP) architecture. Finally\, experimental results show improved execution times on the GPC primarily due to a large decrease in main memory contention. \nShort Bio: Vivek Govindasamy received his Bachelor of Technology degree in Electrical Engineering from Vellore Institute of Technology\, India in 2020\, and M.S. degree in Computer Engineering from the University of California Irvine\, Irvine\, CA\, USA in 2022. He is currently pursuing his PhD degree in Computer Engineering under the supervision of Professor Rainer Doemer. His research is focused on modeling and simulation of many-core computer architectures.
URL:https://www.cecs.uci.edu/event/modeling-and-evaluation-of-a-cache-less-grid-of-processing-cells/
LOCATION:EH 3206\, Engineering Hall University of California\, Irve\, Irvine\, CA\, 92697\, United States
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250514T110000
DTEND;TZID=America/Los_Angeles:20250514T120000
DTSTAMP:20250513T184214Z
CREATED:20250512T171811Z
LAST-MODIFIED:20250513T184214Z
UID:16450-1747220400-1747224000@www.cecs.uci.edu
SUMMARY:In-Memory Computing to Accelerate Machine Learning
DESCRIPTION:Name: Mariam Rakka \nChair: Prof. Fadi Kurdahi \nDate: May 14\, 2025 \nTime: 11:00 AM \nLocation: EH 2430 \nCommittee: Prof. Nikil Dutt\, Prof. Rainer Döemer \nTitle: In-Memory Computing to Accelerate Machine Learning \nAbstract: The increasing computational demands of Machine Learning (ML) models have made conventional computing architectures inadequate due to energy inefficiencies and data movement bottlenecks. In-memory computing (IMC) offers a promising alternative by enabling computation directly within memory arrays. This dissertation presents novel architectural and algorithmic strategies to accelerate machine learning inference using IMC. It proposes precision-fluid data flows and hardware/software co-design techniques to efficiently accelerate different ML workloads. Performance evaluations demonstrate that IMC-based designs can deliver substantial improvements in energy efficiency and throughput\, making them viable candidates for next-generation AI systems. \nBio: Mariam Rakka received her B.E. degree in Computer and Communications Engineering with high distinction from the American University of Beirut\, Lebanon\, in 2020\, along with two minors in Mathematics and Business Administration. She received her M.S. degree in Electrical and Computer Engineering from the University of California\, Irvine\, in 2022. She is currently pursuing her Ph.D. degree in Electrical and Computer Engineering at the University of California\, Irvine under the mentorship of Professor Fadi J. Kurdahi. Her research interests include systems for machine learning and hardware/software co-design. She has completed research internships at Arm in 2022\, 2023\, and 2024\, where she contributed to the design of future generations of ARM processors. She has published in top-tier journals and conferences and served as a reviewer for several peer-reviewed journals in the field.
URL:https://www.cecs.uci.edu/event/in-memory-computing-to-accelerate-machine-learning/
LOCATION:EH 2430\, Engineering Hall\, University of California\, Irvine\, Irvine\, CA\, 92697\, United States
CATEGORIES:PhD Defenses
ATTACH;FMTTYPE=image/jpeg:https://cecs.uci.edu/files/2025/05/mariam_rakka.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250610T090000
DTEND;TZID=America/Los_Angeles:20250610T100000
DTSTAMP:20260120T201804Z
CREATED:20260120T201633Z
LAST-MODIFIED:20260120T201804Z
UID:16676-1749546000-1749549600@www.cecs.uci.edu
SUMMARY:Full-Stack Resource Management for Predictable and Scalable Autonomous Vehicle Pipelines
DESCRIPTION:Name: Dongjoo Seo \nChair: Prof. Nikil Dutt \nDate: June 10\, 2025 \nTime: 9:00 AM \nLocation: DBH 3011 \nCommittee: Prof. Tony Givargis\, Prof. Sang-Woo Jun \nTitle: Full-Stack Resource Management for Predictable and Scalable Autonomous Vehicle Pipelines \nAbstract: Autonomous vehicles (AVs) rely on tightly coupled perception\, planning\, and control pipelines that demand both high throughput and deterministic performance from the underlying computing platform. In the first part of this dissertation\, we address unpredictable memory-induced latency by introducing two complementary strategies. ProSwap leverages periodic access patterns to proactively swap pages before they incur page‐fault penalties\, reducing end‐to‐end pipeline stalls by up to 26% over Linux’s default swapping. Building on this\, MemScape employs reinforcement‐learning driven demotion and promotion across DRAM and high‐capacity memory tiers to avoid latency spikes—trading minimal peak performance for a 3× improvement in tail‐latency stability under dynamic AV workloads. In the second part\, we tackle I/O and CPU resource management challenges that further impact AV real‐time guarantees. SPEED replaces ROS’s single‐queue architecture with a multi‐queue\, context‐aware I/O scheduler\, achieving an 84% reduction in rosbag latency and a 1.5× gain in throughput by aligning writebacks with application idle periods. To eliminate scheduling jitter\, SCHED distills an offline‐trained reinforcement learning policy into a lightweight decision tree for in‐kernel CPU dispatch\, offering up to 250× faster decision times compared to raw RL inference. Together\, these full‐stack optimizations enable scalable\, predictable\, and safe operation of AV pipelines on commodity Linux platforms. \nBio: Dongjoo Seo received his B.E. in Computer Science and Master’s in Computer Software Engineering from Kookmin University at Seoul\, Korea in 2017 and 2020\, respectively. During this Master’s\, Seo worked alongside Prof. Nikil Dutt at UCI as a visiting researcher where he built the simulator system for Fog computing and made a reinforcement learning-based agent for offloading the task. In 2021\, Seo returned to UCI under Prof. Dutt to pursue his Ph.D. in Computer Science. His research focused on specializing OS\, memory systems\, and CLX. Now\, Seo is a software engineer at Samsung Semiconductor\, building reliable next-generation computing platforms for machine learning.
URL:https://www.cecs.uci.edu/event/full-stack-resource-management-for-predictable-and-scalable-autonomous-vehicle-pipelines/
LOCATION:DBH 3011\, Donald Bren Hall University of California\, Irve\, Irvine\, CA\, 92617\, United States
CATEGORIES:PhD Defenses
ATTACH;FMTTYPE=image/jpeg:https://cecs.uci.edu/files/2026/01/Dongjoo_Seo-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260302T130000
DTEND;TZID=America/Los_Angeles:20260302T140000
DTSTAMP:20260305T195727Z
CREATED:20260305T195727Z
LAST-MODIFIED:20260305T195727Z
UID:16729-1772456400-1772460000@www.cecs.uci.edu
SUMMARY:A Pareto-Optimal Compiler for Mapping Task Graphs to Truly Scalable Grids of Processing Cells
DESCRIPTION:Name: Yutong Wang \nChair: Prof. Rainer Doemer \nDate: March 2\, 2026 \nTime: 1:00 PM \nLocation: EH 3206 \nCommittee: Prof. Brian Demsky\, Prof. Zhou Li \nTitle: A Pareto-Optimal Compiler for Mapping Task Graphs to Truly Scalable Grids of Processing Cells \nAbstract: Programming scalable system-on-chip architectures composed of processor arrays remains challenging due to the complexity of partitioning applications\, assigning tasks and data\, and realizing communication under strict locality constraints. Regular grid-based architectures offer scalability and predictable communication\, yet mapping real applications onto such platforms is often manual\, error-prone\, and difficult to validate. This dissertation presents the Grid of Processing Cells Compiler (GPCC)\, an automated framework that maps application task graphs extracted from C++ specifications onto a truly scalable two-dimensional grid of processing cells with local memories and neighbor-only communication. GPCC automatically analyzes application graphs\, performs task and data partitioning\, places tasks onto grid locations\, and generates consistent on-chip and off-chip communication\, producing executable SystemC TLM-2.0 architecture models for system-level simulation and evaluation. GPCC employs a two-level mapping strategy in which tasks are first placed onto processing cells using a dependency-aware recursive search\, followed by assignment of communication channels and external I/O resources. In addition\, this work introduces an automated design space exploration method that evaluates candidate grid dimensions and identifies Pareto-optimal configurations. Experimental results on embedded applications and synthetic benchmarks demonstrate that GPCC efficiently produces correct executable models\, enables systematic exploration of grid-based architectures\, and determines suitable grid dimensions with minimal manual effort. \nBio: Yutong Wang is a Ph.D. candidate in Computer Engineering at UC Irvine\, working in scalable system-on-chip architectures and SystemC-based modeling. His research centers on automated mapping and design space exploration for grid-based processor arrays through the Grid of Processing Cells Compiler (GPCC).
URL:https://www.cecs.uci.edu/event/a-pareto-optimal-compiler-for-mapping-task-graphs-to-truly-scalable-grids-of-processing-cells/
LOCATION:EH 3206\, Engineering Hall University of California\, Irve\, Irvine\, CA\, 92697\, United States
CATEGORIES:PhD Defenses
ATTACH;FMTTYPE=image/webp:https://cecs.uci.edu/files/2026/03/yutong.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260518T130000
DTEND;TZID=America/Los_Angeles:20260518T140000
DTSTAMP:20260824T233918Z
CREATED:20260824T233717Z
LAST-MODIFIED:20260824T233918Z
UID:16893-1779109200-1779112800@www.cecs.uci.edu
SUMMARY:Securing Cyber-Physical Systems: From Sensor-Layer Attacks to Firmware Binary Analysis
DESCRIPTION:Name: Yonatan Gizachew Achamyeleh \nChair: Mohammad Al Faruque\nMember: Zhou Li\nMember: Yasser Shoukry \nDate: 05/18/2026\nTime: 01:00 PM PT\nLocation: ISEB 1010 \nTitle: Securing Cyber-Physical Systems: From Sensor-Layer Attacks to Firmware Binary Analysis\nAbstract: This dissertation advances security across the full stack of cyber-physical systems\, from the physical sensor layer to the firmware binary layer. Four contributions demonstrate that sensors are a pervasive and underprotected attack surface\, showing that pressure sensors can be exploited to eavesdrop on nearby audio\, acoustic signals can destabilize UAV flight\, physical sensor corruption misaligns Vision-Language Model-driven robots\, and sensor rate of change can trigger hardware Trojans covertly. Three further contributions develop tools for semantic recovery from stripped industrial firmware\, spanning binary embeddings\, function name prediction\, and LLM-guided decompilation\, achieving over 94% recompilability across six architectures. The unifying argument is that the sensor and binary layers are structurally coupled\, and that securing one requires understanding the other. \nBio: Yonatan Gizachew Achamyeleh is a PhD candidate in Computer Engineering at the University of California\, Irvine\, advised by Professor Mohammad Abdullah Al Faruque. His research spans cyber-physical systems security\, embedded binary analysis\, and the intersection of physical-layer attacks with AI-driven autonomy.
URL:https://www.cecs.uci.edu/event/securing-cyber-physical-systems-from-sensor-layer-attacks-to-firmware-binary-analysis/
LOCATION:CA
CATEGORIES:PhD Defenses
ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2026/08/Yonatan-Achamyeleh.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260608T100000
DTEND;TZID=America/Los_Angeles:20260608T110000
DTSTAMP:20260716T025310Z
CREATED:20260716T025012Z
LAST-MODIFIED:20260716T025310Z
UID:16853-1780912800-1780916400@www.cecs.uci.edu
SUMMARY:Adaptive Sparsity for Efficient and Reliable Machine Learning Inference in Autonomous Vehicles
DESCRIPTION:Name: Danny Abraham \nChair: Prof. Nikil Dutt \nDate: June 8\, 2026 \nTime: 10:00 AM \nLocation: DBH 4011 \nCommittee: Prof. Fadi Kurdahi\, Prof. Mohsen Imani \nTitle: Adaptive Sparsity for Efficient and Reliable Machine Learning Inference in Autonomous Vehicles \nAbstract: Autonomous vehicles rely on machine learning models that must make accurate decisions under strict latency\, memory\, and reliability constraints. However\, modern deep learning systems are often designed as fixed\, dense inference pipelines\, even though real driving conditions vary across compute availability\, scene difficulty\, sensor structure\, and modality access.\nThis dissertation presents adaptive sparsity as a framework for making autonomous vehicle inference more efficient and responsive to these changing conditions. It explores three complementary forms of sparsity: parameter sparsity for dynamically adjusting model capacity\, activation sparsity for exploiting input-dependent computation\, and input sparsity for using rich training-time modalities to improve deployment-time models with fewer inputs. Together\, these methods show how sparsity can serve not only as a compression tool\, but as a mechanism for adaptive\, efficient\, and reliable inference in autonomous vehicle systems. \nBio: Danny Abraham is a PhD student in the School of Computer Science at UC Irvine\, working with Dr. Nikil Dutt\, in the field of embedded machine learning. His current line of work is researching adaptive machine learning models for resource-constrained embedded systems\, focusing on dynamic runtime reconfiguration. This enables real-time model adjustment and optimizes the tradeoff between accuracy\, latency\, and energy consumption particularly in the context of autonomous vehicles.
URL:https://www.cecs.uci.edu/event/adaptive-sparsity-for-efficient-and-reliable-machine-learning-inference-in-autonomous-vehicles/
LOCATION:DBH 4011\, Donald Bren Hall\, University of California\, Irvine\, Irvine\, CA\, 92617\, United States
CATEGORIES:PhD Defenses
ATTACH;FMTTYPE=image/jpeg:https://cecs.uci.edu/files/2026/07/danny.jpg
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