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DTSTART;TZID=America/Los_Angeles:20040402T150000
DTEND;TZID=America/Los_Angeles:20040402T160000
DTSTAMP:20231011T184637Z
CREATED:20231011T184637Z
LAST-MODIFIED:20231011T184637Z
UID:14343-1080918000-1080921600@www.cecs.uci.edu
SUMMARY:System-Level Automatic Model Refinement
DESCRIPTION:System-Level Automatic Model Refinement\nby Junyu Peng \nIn a system-level design methodology\, the system under design is represented by models at different abstraction levels. The design process is essentially a series of steps that gradually transform the most abstract specification model into a detailed implementation model. In practice\, all these models are written manually by designers. As the result\, the designers spend long time on this tedious and error-prone model-writing task. In addition\, it is not possible to verify the equivalence between the models written manually. In this dissertation we present our work on automatic model generation\, where models are generated automatically by tools rather than manually by designers. This kind of automation not only relieves designers from the mundane and time-consuming coding task but also makes it possible to formally verify the functional equivalence between models. \nThis dissertation in particular focuses on the architecture refinement\, which is aimed to automatically generate an architecture model from the input specification model after architecture exploration when architecture allocation and partitioning decisions are made. We approach the problem by first formally defining the semantics and styles of the input specification model and the output architecture model. Based on the differences between the input and output models\, we are able to define a refinement flow which consist of a series of formally-defined transformations. \nDistinguishing itself from other similar approaches\, our approach addresses the quality issue of the automatically generated models. We defined a set of quality metrics that are relevant to architecture refinement. Then we devised several optimization algorithms which can be embedded into the transformations to improve the quality of the output model. \nIn order to prove the feasibility of our approach\, we implemented an automatic model refinement engine which is targeted at the SpecC language. We validated the effectiveness of our approach by applying the refinement engine to a couple of large\, real-life applications. Experimental results demonstrate that 1000x productivity gain is achievable with automatic model generation.
URL:https://www.cecs.uci.edu/event/system-level-automatic-model-refinement/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040319T150000
DTEND;TZID=America/Los_Angeles:20040319T160000
DTSTAMP:20231011T184637Z
CREATED:20231011T184637Z
LAST-MODIFIED:20231011T184637Z
UID:14344-1079708400-1079712000@www.cecs.uci.edu
SUMMARY:Specification-driven Validation of Programmable Embedded Systems
DESCRIPTION:Specification-driven Validation of Programmable Embedded Systems\nby Prabhat Mishra\nValidation of programmable embedded systems\, consisting of processor cores\, coprocessors\, and memory subsystems\, is one of the major bottlenecks in current System-on-Chip (SOC) design methodology. One of the most important problems in validation of such systems is the lack of a golden reference model. As a result\, many existing validation techniques employ a bottom-up approach to design verification\, where the functionality of an existing architecture is\, in essence\, reverse-engineered from its implementation. \nThis thesis presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification. We have developed validation techniques to ensure that the static and dynamic behaviors of the specified architecture are well formed. The validated specification is used as a golden reference model. \nA major challenge in top-down validation methodology is the ability to generate executable models from the specification for a wide variety of programmable architectures. We have developed a functional abstraction technique that enables specification-driven model generation for simulation\, hardware generation\, and property checking. The generated simulator and hardware models are used for design space exploration of programmable architectures. \nWe have explored two top-down validation scenarios: design validation and test generation. First\, the generated hardware is used as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. Second\, we have proposed a functional coverage based test generation technique for validation of pipelined processor architectures. The experiments demonstrate the utility of the specification-driven validation methodology for programmable embedded systems.
URL:https://www.cecs.uci.edu/event/specification-driven-validation-of-programmable-embedded-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040127T150000
DTEND;TZID=America/Los_Angeles:20040127T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14348-1075215600-1075219200@www.cecs.uci.edu
SUMMARY:System-Level Design Methodology
DESCRIPTION:Presented by Professor Daniel Gajski\, University of California\, Irvine\nASP-DAC 2004\nPacifico Yokohama\, Yokohama\, Japan\nJanuary 27\, 2004\ndownload pdf
URL:https://www.cecs.uci.edu/event/system-level-design-methodology/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031219T150000
DTEND;TZID=America/Los_Angeles:20031219T160000
DTSTAMP:20231011T184638Z
CREATED:20231011T184638Z
LAST-MODIFIED:20231011T184638Z
UID:14345-1071846000-1071849600@www.cecs.uci.edu
SUMMARY:Estimation and Exploration Automation of System Level Design
DESCRIPTION:Estimation and Exploration Automation of System Level Design\nby Lukai Cai\nRecently\, as system design is becoming more and more challenging due to decreasing timeto-\nmarket and increasing system complexities\, trends are emerging to move the design process to\nhigher levels of abstraction. System-level design demands corresponding approaches that efficiently explore the complete system design space and rapidly evaluate a large number of design alternatives in a short amount of time. \nThis work proposes fast estimation and efficient exploration approaches for system synthesis\ndesign flow. It starts with the system behavior which represents the design functionality\, generates\nthe system architecture from the system behavior\, and finally maps the system behavior to the\nsystem architecture. \nIn this work\, we target at complex system design: the system behavior is modeled concurrently\nand hierarchically\, the system architecture is assembled by processing elements with\ndifferent attributes and incompatible communication protocols. Because our approaches are all\nimplemented at high abstraction levels and have relatively low time complexities\, we meet the\nrequirement for fast estimation and exploration of the system level design.
URL:https://www.cecs.uci.edu/event/estimation-and-exploration-automation-of-system-level-design/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031120T150000
DTEND;TZID=America/Los_Angeles:20031120T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14349-1069340400-1069344000@www.cecs.uci.edu
SUMMARY:System Debugging and Verification: A New Challenge
DESCRIPTION:Presented by Professor Daniel Gajski and Samar Abdi\, University of California\, Irvine\nVerify 2003\nNovember 20\, 2003\ndownload pdf
URL:https://www.cecs.uci.edu/event/system-debugging-and-verification-a-new-challenge/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031107T150000
DTEND;TZID=America/Los_Angeles:20031107T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14350-1068217200-1068220800@www.cecs.uci.edu
SUMMARY:Covalidation of Hardware/Software Systems
DESCRIPTION:Presented by Professor Ian G. Harris\, University of California\, Irvine\nIntel Test Research Symposium\nSanta Clara\, CA\nNovember 7\, 2003\ndownload pdf
URL:https://www.cecs.uci.edu/event/covalidation-of-hardware-software-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020826T150000
DTEND;TZID=America/Los_Angeles:20020826T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14351-1030374000-1030377600@www.cecs.uci.edu
SUMMARY:Design Methodology for Systems-On-Chip
DESCRIPTION:Presented by Professor Daniel Gajski\, University of California\, Irvine\nIEEE Orange County Computer Society\nWyndham Gardens Hotel\, Costa Mesa\, CA\nAugust 26\, 2002\ndownload pdf
URL:https://www.cecs.uci.edu/event/design-methodology-for-systems-on-chip/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
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