BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250311T100000
DTEND;TZID=America/Los_Angeles:20250311T110000
DTSTAMP:20250310T202338Z
CREATED:20250310T202256Z
LAST-MODIFIED:20250310T202338Z
UID:16415-1741687200-1741690800@www.cecs.uci.edu
SUMMARY:Modeling and Evaluation of a Cache-less Grid of Processing Cells
DESCRIPTION:Name: Vivek Govindasamy \nChair: Prof. Rainer Doemer \nDate: March 11\, 2025 \nTime: 10:00 AM \nLocation: EH 3206 (CECS Conference Room) \nCommittee: Prof. Mohammad Al Faruque\, Prof. Ian Harris \nTitle: Modeling and Evaluation of a Cache-less Grid of Processing Cells \nAbstract: Modern processors experience memory contention when the speed of their computational units exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory wall and is a great challenge in computer engineering. The reason for this phenomenon is the unequal growth rate in memory access speeds compared to processor clock rates. In order to mitigate the memory bottleneck in classic computer architectures\, a scalable parallel computing platform called the Grid of Processing Cells (GPC) has been proposed. To evaluate its effectiveness\, we model the GPC in this work at the instruction-level and functional-level using SystemC TLM-2.0\, with a focus on memory contention. In an advanced model\, individual GPC cells can be switched as needed between the two abstraction levels. We then show that our mixed-level system model enables fast and accurate simulations. We test multiple streaming applications on the GPC\, analyze software-based optimization methods and their effects on the GPC\, at both abstraction levels. The performance is then compared against the traditional shared memory processor (SMP) architecture. Finally\, experimental results show improved execution times on the GPC primarily due to a large decrease in main memory contention. \nShort Bio: Vivek Govindasamy received his Bachelor of Technology degree in Electrical Engineering from Vellore Institute of Technology\, India in 2020\, and M.S. degree in Computer Engineering from the University of California Irvine\, Irvine\, CA\, USA in 2022. He is currently pursuing his PhD degree in Computer Engineering under the supervision of Professor Rainer Doemer. His research is focused on modeling and simulation of many-core computer architectures.
URL:https://www.cecs.uci.edu/event/modeling-and-evaluation-of-a-cache-less-grid-of-processing-cells/
LOCATION:EH 3206\, Engineering Hall University of California\, Irve\, Irvine\, CA\, 92697\, United States
CATEGORIES:PhD Defenses
END:VEVENT
END:VCALENDAR