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DTSTART;TZID=America/Los_Angeles:20180503T150000
DTEND;TZID=America/Los_Angeles:20180503T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14517-1525359600-1525363200@www.cecs.uci.edu
SUMMARY:"Efficient Acceleration of Computation Using Associative In-memory Processing"
DESCRIPTION:Title: “Efficient Acceleration of Computation Using Associative In-memory Processing”\nSpeaker: Hasan Erdem Yantir\, University of California\, Irvine \nDate and Time: Monday\, May 14\, 2018 at 9:00AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi (Chair)\, Ahmed Eltawil\, Rainer Doemer \nAbstract: \nThe complexity of the computational problems is rising faster than the computational platforms’ capabilities. This forces researchers to find alternative paradigms and methods for efficient computing. One promising paradigm is accelerating compute-intensive kernels using in-memory computing accelerators since memory is the major bottleneck that limits the amount of parallelism and performance of a system and dominates energy consumption in computation. Leveraging the memory intensive nature of big data applications\, an in-memory-based computation system can be presented where logic can be replaced by memory structures\, virtually eliminating the need for memory load/store operations during computation. The massive parallelism enabled by such a paradigm results in highly scalable structures. \nThe present thesis is studied against this background. The objective is to conduct a broad perspective research on in-memory computing. For this purpose\, associative computing architectures (i.e.\, Associative Processors\, or AP) are built by both traditional (SRAM) and emerging (ReRAM) memory technologies together with their corresponding software frameworks. For ReRAM-based APs\, the reliability concerns coming with the emerging memories are resolved. Architectural innovations are developed to increase the energy efficiency. Furthermore\, approximate computing approach is introduced for APs to perform efficient/low-power approximate in-memory computing for the tasks which can tolerate some accuracy lost.  The works also propose a novel two-dimensional in-memory computing architecture to cope with the existing deficiencies of the traditional one-dimensional AP architectures.
URL:https://www.cecs.uci.edu/event/efficient-acceleration-of-computation-using-associative-in-memory-processing/
CATEGORIES:PhD Defenses
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DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14525-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:SIMD Assisted Fault Detection and Fault Attack Mitigation
DESCRIPTION:Name: Zhi Chen\nDate: May 15\, 2018 \nTime: 2:30pm \nLocation: Donald Bren Hall 3011 \nCommittee: Professor Alex Nicolau (Chair)\, Alex Veidenbaum\, Nikil Dutt \nAbstract: \nModern processors continue to aggressively scale down the feature size and reduce voltage levels to run faster and be more energy efficient. However\, this trend also poses significant reliability concern as it makes transistors more susceptible to soft errors. Soft errors are transient. Although they don’t impair the computing systems permanently\, these errors can corrupt the output of a program or even crash the entire system. Hardware or software redundant techniques could be used to detect errors during the execution of a program. However\, hardware redundancy\, e.g. DMR (dual-modular redundancy) and TMR (triple-modular redundancy)\, leads to significant area overhead and very high energy cost. Software redundancy\, e.g. instruction duplication\, has lower performance and energy penalty and  virtually no hardware cost by sacrificing a small degree of error coverage. Yet commodity processors generally don’t require “five-nines” reliability as they are not mission-critical. Instead\, performance and energy consumption have more priority. This dissertation proposes a novel approach to instruction duplication\, which exploits the redundancy within SIMD instructions. The key idea is to pack the original data and its duplicate in the different lanes of the same vector register instead of executing two scalar instructions separately as these registers are underutilized on most applications. The proposed solution is implemented in the LLVM compiler as a stand-alone pass. Evaluation on a host of benchmarks reveal that proposed SIMD-based error detection technique causes much less performance\, code size\, and energy overheads.\n\nThis dissertation further extends the proposed approach as a countermeasure to protect cryptographic algorithms. These algorithms are widely adopted in modern processors and embedded systems to protect information. A number of popular cryptographic algorithms in the Libgcrypt library are protected using the SIMD-based instruction duplication technique. A large amount of errors are injected to these algorithms. The results show that almost all injected faults can be detected with reasonable performance and code size cost.\n 
URL:https://www.cecs.uci.edu/event/simd-assisted-fault-detection-and-fault-attack-mitigation/
CATEGORIES:PhD Defenses
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180517T150000
DTEND;TZID=America/Los_Angeles:20180517T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14526-1526569200-1526572800@www.cecs.uci.edu
SUMMARY:Reflective On-Chip Resource Management Policies for Energy-Efficient Heterogeneous Multiprocessors
DESCRIPTION:Name: Tiago Mück\nDate: May 16\, 2018 \nTime: 2:00pm \nLocation: Donald Bren Hall 2011 \nCommittee: Nikil Dutt (Chair)\, Alex Nicolau\, Tony Givargis \nAbstract: \nEffective exploitation of power-performance tradeoffs in heterogeneous many-core platforms (HMPs)\, requires intelligent on-chip resource management at different layers\, in particular at the operating system level. Operating systems need to continuously analyze the application behavior and find a proper answer for questions such as: What is the most power efficient core type to execute the application without violating its performance requirements? or Which option is more power-efficient for the current application: an out-of-order core at a lower frequency or an inorder core at a higher frequency?\nUnfortunately\, existing operating systems (e.g. Linux) do not offer mechanisms to properly address these questions and therefore are unable to fully exploit architectural heterogeneity for scalable energy-efficient execution of dynamic workloads.\nThis dissertation proposes a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software.\n\nThe general idea of reflection is to change your actions based on both external feedback and introspection (i.e.\, self-assessment).\n\n\nFrom a practical computer system perspective\, reflection means performing resource management actions considering both sensing information (e.g.\, readings from performance counters\, power sensors\, etc.) to assess the current system state\, as well as models to predict the behavior of the system before performing an action.\nIn this context\, this dissertation describes MARS\, a Middleware for Adaptive Reflective computer Systems. MARS consists of a framework and a set of models for creating reflective resource managers. MARS is implemented and evaluated on top a real Linux-based platform. Furthermore\, MARS also provides an offline simulation infrastructure for fast prototyping of policies and large-scale or long-term policy evaluation.\n\nExperimental evaluation shows that MARS’s models allow different policies for task mapping and dynamic voltage scaling to be seamlessly integrated\, resulting in up-to 1.8x energy efficiency improvements without performance degradation when compared to vanilla Linux.
URL:https://www.cecs.uci.edu/event/reflective-on-chip-resource-management-policies-for-energy-efficient-heterogeneous-multiprocessors/
CATEGORIES:PhD Defenses
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