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20th IEEE International Parallel & Distributed
Processing Symposium
April 25-29, 2006
Rhodes Island, Greece

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Technical Committee on
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Reconfigurable Architectures Workshop - RAW

 

Workshop Introduction - RAW
 

RAW Keynote 1: The Outer Limits: Reconfigurable Computing in Space and In Orbit
Maya Gokhale

RAW Keynote 2: New Horizons of Very High Performance Computing (VHPC): Hurdles and Chances
Reiner Hartenstein

Analysis of a Reconfigurable Network Processor
Christoforos Kachris, Stamatis Vassiliadis

Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor
Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura , Hideharu Amano

2D Defragmentation Heuristics for Hardware Multitasking on Reconfigurable Devices
Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero

A Cost-Effective Context Memory Structure for Dynamically Reconfigurable Processors
Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano

Performance of FPGA Implementation of Bit-split Architecture for Intrusion Detection Systems
Hong-jip Jung, Zachary K. Baker, Viktor K. Prasanna

A Configuration Memory Hierarchy for Fast Reconfiguration with Reduced Energy Consumption Overhead
Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor

Maximum Edge Matching for Reconfigurable Computing
Markus Rullmann, Renate Merker

FPGA Implementation of a License Plate Recognition SoC using Automatically Generated Streaming Accelerators
Nikolaos Bellas, Sek Chai, Malcolm Dwyer, Dan Linzmeier

A High-level Target-precise Model for Designing Reconfigurable HW Tasks
Maik Boden, Steffen Ruelke, Jürgen Becker

Rapid Development of High Performance Floating-Point Pipelines for Scientific Simulation
Gerhard Lienhart, Andreas Kugel, Reinhard Männer

An Optimal Architecture for a DDC
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Smit

Reconfigurable Memory Based AES Co-Processor
Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa

Communication Concept for Adaptive Intelligent Run-Time Systems Supporting Distributed Reconfigurable Embedded Systems
Michael Ullmann, Jürgen Becker

FPGA based Architecture for DNA Sequence Comparison and Database Search
Euripides Sotiriades, Christos Kozanitis, Apostolos Dollas

Accelerating DTI Tractography using FPGAs
Aditya Kwatra, Viktor Prasanna, Manbir Singh

An Adaptive System-on-Chip for Network Applications
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle

Dedicated Module Access in Dynamically Reconfigurable Systems
J. Hagemeyer, B. Kettelhoit, M. Porrmann

Exploiting dynamic reconfiguration of platform FPGAs: Implementation issues
Miguel L. Silva, João Canas Ferreira

A Distributed Object System Approach for Dynamic Reconfiguration
Ronald Hecht, Stephan Kubisch, Harald Michelsen, Elmar Zeeb, Dirk Timmermann

Elementary Block Based 2-Dimensional Dynamic and Partial Reconfiguration for Virtex-II FPGAs
Michael Hübner, Christian Schuck, Jürgen Becker

Physically-aware Exploitation of Component Reuse in a Partially Reconfigurable Architecture
Love Singhal, Elaheh Bozorgzadeh

Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware
Klaus Danne, Marco Platzner

A Pattern Selection Algorithm for Multi-Pattern Scheduling
Yuanqing Guo, Cornelis Hoede, Gerard J.m. Smit

Mapping DSP Applications on Processor Systems with Coarse-Grain Reconfigurable Hardware
Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis

VoC: A Reconfigurable Matrix for Stereo Vision Processing
Ricardo Pezzuol Jacobi, Renato Barreto Cardoso, Geovany Borges

Selection of Instruction Set Extensions for an FPGA Embedded Processor Core
Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones

Dynamic Configuration Steering for a Reconfigurable Superscalar Processor
Nick A. Mould, Brian F. Veale, Monte P. Tull, John K. Antonio

Automatic Application-Specific Microarchitecture Reconfiguration
Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood

Accelerating CABAC Encoding for Multi-standard Media with Configurability
Oskar Flordal, Di Wu, Dake Liu

Exploiting Processing Locality through Paging Configurations in Multitasked Reconfigurable Systems
Mohamed Taher, Tarek El-Ghazawi

Investigation into Programmability for Layer 2 Protocol Frame Delineation Architectures
Ciaran Toal, Sakir Sezer

Multi-level Reconfigurable Architectures in the Switch Model
Sebastian Lange, Martin Middendorf

Platform-based FPGA Architecture: Designing High-Performance and Low-Power Routing Structure for Realizing DSP Applications
Konstantinos Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis

Multi-Clock Pipelined Design of an IEEE 802.11a Physical Layer Transmitter
Maryam Mizani, Daler Rakhmatov

On-chip and On-line Self-Reconfigurable Adaptable Platform: the Non-Uniform Cellular Automata Case
Andres Upegui, Eduardo Sanchez

Increasing Analog Programmability in SoCs
Erik Schüler, Luigi Carro

Partial and dynamic Reconfiguration of FPGAs : a top down design methodology for an automatic implementation
Florent Berthelot, Fabienne Nouvel, Dominique Houzet

Architecture of a Multi-Context FPGA Using a hybrid Multiple-Valued/Binary Context Switching Signal
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama

A High Level SoC Power Estimation Based on IP Modeling
David Elleouet, Nathalie Julien, Dominique Houzet

Implementation of a Reconfigurable Hard Real-Time Control System for Mechatronic and Automotive Applications
Steffen Toscher, Roland Kasper, Thomas Reinemann

Run-Time Reconfiguration of Communication in SIMD Architectures
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter Jonker

Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time
Sascha Uhrig, Stefan Maier, Georgi Kuzmanov, Theo Ungerer

Reconfiguration of Embedded Java Applications
João Cláudio Soares Otero, Flávio Rech Wagner, Luigi Carro

Speech Silicon AM: An FPGA-Based Acoustic Modeling Pipeline for Hidden Markov Model based Speech Recognition
Jeffrey W. Schuster, Raymond Hoare, Kshitij Gupta

Implementation of a Programmable Array Processor Architecture for Approximate String Matching Algorithms on FPGAs
Panagiotis D. Michailidis, Konstantinos G. Margaritis

ReConfigME: A Detailed Implementation of an Operating System for Reconfigurable Computing
Grant Wigley, David Kearney, Mark Jasiunas

An Automated Development Framework for a RISC Processor with Reconfigurable Instruction Set Extensions
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis

High-Level Synthesis with Reconfigurable Datapath Components
George Economakos

An Optically Differential Reconfigurable Gate Array with a Holographic Memory
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi

A Stochastic Multi-Objective Algorithm for the Design of High Performance Reconfigurable Architectures
Wing On Fung, Tughrul Arslan

Reconfigurable Communications for Image Processing Applications
André Borin Soares, Luigi Carro, Altamiro Amadeu Susin

Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup
Kieran Mclaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias Noll, John McCanny

RTOS Extensions for Dynamic Hardware / Software Monitoring and Configuration Management.
Yvan Eustache, Jean-Philippe Diguet, Milad El Khodary

Securing Embedded Programmable Gate Arrays in Secure Circuits
Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frederic Bancel

Design Space Exploration for Low-Power Reconfigurable Fabrics
Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones

Exploiting Dynamic Reconfiguration Techniques: The 2D-VLIW Approach
Ricardo Santos, Rodolfo Azevedo, Guido Araujo

Applying Single Processor Algorithms to Schedule Tasks on Reconfigurable Devices Respecting Reconfiguration Times
Florian Dittmann, Marcelo Götz

Dynamically Reconfigurable Cache Architecture Using Adaptive Block Allocation Policy
Milene Barbosa Carvalho, Luís Fabrcio Wanderley Góes, Carlos Augusto Paiva Da Silva Martins

Practical Design of a Computation and Energy Efficient Hardware Task Scheduler in Embedded Reconfigurable Computing Systems
Tyrone Tai-on Kwok, Yu-kwong Kwok

Reconfigurable Context-Free Grammar Based Data Processing Hardware with Error Recovery
James Moscola, Young H. Cho, John W. Lockwood

Power Consumption Advantage of a Dynamic Optically Reconfigurable Gate Array
Minoru Watanabe, Fuminori Kobayashi

VHDL to FPGA automatic IPCore generation: A case study on Xilinx design flow
Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco Domenico Santambrogio

 

 

 

 

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