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FAT: Fast and Accurate Transaction-Level Modeling
The field of embedded systems increasingly extends to more complex scenarios including safety critical systems. Distributed embedded real-time systems with many processors become necessary. Accurate communication modeling is an important issue for the design of those complex systems. However, efficient system level design requires also high execution performance especially for communication models.
Recent research work introduced Transaction Level Modeling as a means of increasing the simulation performance. Here, large speed-up is gained by abstracting away communication details. Inevitably this results in a loss of simulation accuracy. However, due to the complexity of accuracy measurements and its statistical analysis, no clear expressive quantification of the speed-accuracy tradeoff prevails.
The goals of this research project include:
- identification of appropriate performance and accuracy properties for communication models
- definition and statistical analysis of accuracy measurements
- development and definition of modeling styles that yield high execution speed yet maintain required accuracy
- demonstration of benefits using industry bus standards (e.g. AMBA, CAN)
- Gunar Schirner and Rainer Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), accepted for publication, August 23, 2007.
- Gunar Schirner and Rainer Dömer "Quantitative Analysis of Transaction Level Models for the AMBA Bus", In Proceedings of Design Automation and Test in Europe, Munich, Germany, March 2006. pdf, presentation
- Gunar Schirner and Rainer Dömer "Abstract Communication Modeling: A Case Study Using the CAN Automotive Bus", In Proceedings of International Embedded Systems Symposium, "From Specification to Embedded Systems Application" (ed. A. Rettberg, Z. Mauro, F. Rammig), Springer, Manaus, Brazil, Aug. 2005. (Best Paper Award) pdf
ROM: Result Oriented Modeling
Despite our optimistic
title of the previous project "FAT: Fast and Accurate TLM", we analyzed TLMs for many different
bus systems and quantified the TLM trade-off between speed and
accuracy. A model is either fast or accurate for the general case
(although there are cases where a TLM is accurate enough).Now, we introduced ROM: Result Oriented Modeling,
a modeling technique communication TLMs.
ROM can eliminate the inaccuracies for TLM in many cases, yet it is
able to retain the TLM speed advantage. ROM makes the assumption that
an application only needs to observe the timing at a transaction
boundary. On the other hand, everything inside the transaction is
hidden. With this assumption, ROM can rearrange or omit internal states to gain speed. Instead of simulating each bus cycle, ROM makes and optimistic prediction right at the beginning of the transaction. It uses calculates the transaction duration (Answering: How long will this transaction take, if there is no further preemption?). Then, at the end of the predicted time, it checks weather the assumptions did hold true. It updates the prediction, in case there was an unexpected preemption. With that ROM reaches both: speed and accuracy.
Relevant publications:
- Gunar Schirner and Rainer Dömer: "Result Oriented Modeling - A Novel Technique for Fast and Accurate TLM", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1688-1699, Sept. 2007. pdf
- Gunar Schirner and Rainer Dömer "Fast and Accurate Transaction Level Models using Result Oriented Modeling", In Proceedings of the International Conference on Computer Aided Design, San Jose, California, November 2006. pdf, presentation
- Gunar Schirner and Rainer Dömer "Accurate yet Fast Modeling of Real-Time Communication", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Seoul, Korea, October 2006. pdf
Embedded Software Development in a System Level Design Context
System level design is one approach to tackle the complexity of designing a modern System-on-Chip. One major aspect is the capability of developing the system model without a special attention to the later occurring hardware software split. Both hardware and software can be developed seamlessly at the same time. It therefore allows a better integration between those traditionally separated development flows.
Hardware / software co-simulation is needed for an efficient integrated HW/SW development. Depending on the design phase this co-simulation can be done at different levels of abstraction. They range from the very abstract simulation at the specification level down to the cycle accurate simulation of hardware and the software execution on an instruction set simulator.
The first stage of the project is to define a base architecture for future experiments. Due to the wide popularity of the ARM processors (and our availability of the AMBA AHB bus models), we have chosen an instruction set simulator (SWARM) for the ARM7TDMI. We integrated the ISS into the System-on-Chip Design Environment (SCE), which allows us to quickly generate cycle accurate models of custom SoC architectures.
Additionally we have integrated a real-time operating system (MicroC/OS-II by Micrium) to run on top of the ISS. This gives us the ability to explore the real-time implications of the software hardware interaction. We also develop a tool that automatically generates - based on the description in the SLDL - the embedded software and targets the code to a chosen RTOS.
Relevant publications:
- G. Schirner, G. Sachdeva, A. Gerstlauer, R. Dömer: "Embedded Software Development in a System-level Design Flow", Proceedings of the International Embedded Systems Symposium, "Embedded System Design: Topics, Techniques and Trends" (ed. A. Rettberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Rammig), Springer, Irvine, California, May 2007. pdf
- Gunar Schirner, Andreas Gerstlauer and Rainer Dömer "Abstract Multifaceted Modeling of Embedded Processors for System-Level Design", Proceedings of the Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, January 2007. pdf, presentation