Welcome to the EECS 31L/CSE 31L Course Web Site

EECS 31L/CSE 31L: Digital Design Laboratory (Winter 2012)

This is a laboratory course in which students learn the design process of modeling, simulation and synthesis of simple digital designs. Students in this class learn how to model designs on different levels of abstraction using C and VHDL languages. The course consists of four labs. In the first lab students are given a simple combinatorial design and then are required to generate VHDL structural and behavioral models and simulate using ModelSim. In the second assignment students produce a simple structural FSM model in VHDL language and learn how to generate it from FSM behavioral model. In the third lab they model a datapath that implements a simple arithmetic formula in a register file. In the last lab the students generate datapath and control units that execute the DCT algorithm and model it by a clock-cycle accurate structural model. In this class students are given the opportunity to be creative and to produce the best possible design for the given constraints.

Since there are only 2 hours of lectures per week and not enough time to cover Hardware Description Languages (such as VHDL or Verilog), simulation principles, modeling concepts and design methodology, we will use the following learning method:

  1. Students will need to refresh their understanding of the digital design methodology from the course on intro to digital design (such as EECS31);
  2. Students are required to watch simulator-tutorial video and familiarize thenmselves with simulation environment (TAs will help with specific questions);
  3. Since teaching all of the VHDL constructs is beyond the scope of this course, students should watch the lecture videos describing the necessary and sufficient VHDL constructs to model design behavior and structure for each lab;
  4. In order to minimize confusion, students will get the template models from the web site with all necessary components included in the template. They will need to submit design models using those components;
  5. Students will submitt behavioral and structural models electronically through EEE web site (extra credit is given for early submissions: see lab handouts);
  6. After submission of models, there will be a short quiz to demonstrate the design and modeling knowledge for each lab assignment.

Additional Course Information

Course Title Introduction to Digital Design Laboratory
Instructor Daniel D. Gajski
Office Location 3207 Engineering Hall
Office Hours After class or by appointment
Lecture Fridays, 3:00 PM - 5:00 PM ELH 100
Labs Mondays, Wednesdays, and Fridays 11:00 AM - 7:50 PM EH 1131
TAs Lab Hours:
  • Xu Han (Email: hanx@uci.edu)
    Wednesdays 10:00 AM - 1:00 PM in EH 1131, and by appointment
  • Yasaman Samei (Email: ysameisy@uci.edu)
    Fridays 9:00 AM - 12:00 PM in EH 1131, and by appointment
  • Quoc-Viet Dang (Email: qpdang@uci.edu)
    Wednesdays 3:00 PM - 6:00 PM in EH 1131 and by appointment
Grader Not assigned
Primary Textbook Frank Vahid and Roman Lysecky, VHDL For Digital Design, John Wiley, 2007.
Design Tool Xilinx ISE and Xilinx ModelSim
Useful References Frank Vahid, Digital Design, John Wiley, 2012.
Daniel D. Gajski, Principles of Digital Design, Prentice Hall, 1997.
Prerequisites EECS31 or CSE31

Videos: