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EECS 31/ICS 151 - Digital Logic Design
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 EECS
31/ICS 151 is the introductory course in digital design. First, students
learn basic concepts of computer science and computational models such as
binary representation, Boolean algebra, finite-state-machine
and instruction-set processors. They also learn basic components for design
on different levels of abstractions such as transistors, gates, flip flops,
adders, multipliers, registers, memories and processors. Secondly, students
learn the basics of design science. That is, how to convert computational
models into working implementations. They learn how to construct adders and
multipliers out of gates, and registers and
counters out of flip-flops and how to optimize them for performance and
cost. Furthermore, they learn how to design basic system components such as
memories, queues, stacks and processors and how to use them in the design
of arbitrary systems. The course stresses the principles of design science
and gives in each lecture clear and simple procedures on how to arrive at
the best design from the given specification.
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EECS 31L / CSE 31L - Digital Design Laboratory
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This is a laboratory course in which students learn the design process of modeling,
simulation and synthesis of simple digital designs. Students in this class
learn how to model designs on different levels of abstraction using C and
VHDL languages. The course consists of four labs. In the first lab students
are given a simple combinatorial design and then are required to generate
VHDL structural and behavioral models and simulate using ModelSim. In the second assignment students define a
simple structural FSM model in VHDL language and learn how to
generate it from behavioral model. In the third lab they optimize the model
hardware implementation of a 8-bit adder/subtractor. In the last lab the students generate datapath and control units that execute the given algorithm
and model it by a clock-cycle accurate structural model. In this class
students are given the opportunity to be creative and to produce the best
possible design for the given constraints.
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ICS 152 - Computer Systems Architecture
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ICS 152 is the basic course in computer architecture. First, students learn
basic concepts of computers and systems design such as instruction sets,
instruction execution cycles, pipelining, multithreading, and
multiprocessing. Second, the students learn basic components of computer
systems such as processor organization, memory architecture, connection
networks and I/O implementation. Thirdly, they learn different
architectural styles such as CISC and RISC processors, superscalar and VLIW
processors, multiprocessors and distributed computers. Students also learn
how to specify a computer system; how to build it from the specification
and how to design its software and hardware components.
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ICS 155B - Computer Design
Laboratory
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This is a laboratory course in which students learn the design process of
converting algorithms into software/hardware designs. Students in this
class learn how to model designs on different levels of abstraction using C
and VHDL languages. The course consists of five labs. In the first lab
students are given a well-known algorithm from DSP or multimedia
applications and then are required to debug C and VHDL specifications or
behavioral models. In the second assignment students complete a clock-cycle
accurate behavioral model of the algorithm in VHDL language and learn how
to generate it from behavioral models. In the third lab they optimize the
model for software and in the fourth they optimize the model for hardware
implementation. In the last lab the students generate databases and control
units that execute the given optimized algorithm and model it by a
clock-cycle accurate structural model. In this class students are given the
opportunity to be creative and to produce the best possible design for the given
constraints.
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ICS 256 - Design Synthesis
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This course is an introduction to hardware synthesis on logic and
register-transfer levels. First, the course deals with synthesis algorithms
for logic synthesis and optimization for performance, cost and power.
Second, the courses addresses the synthesis process from a behavioral
description into a register-transfer (cycle accurate) implementation
consisting of control units and datapaths for
custom and standard processors. The course introduces the topics of
component databases, component allocation, time-constrained and
resource-constrained scheduling, functional unit, memory and bus binding,
design estimation, modeling styles for synthesis, and design environments
for automatic and interactive synthesis, The course also offers an
introduction to common models and design processes for software/hardware codesign.
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ICS 257 - System Tools
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This course deals with specification and design of embedded systems. The
course starts with different models of computations and requirements for
embedded systems. It then gives a survey of specification languages for
generating executable specification for embedded systems. Furthermore, the
course covers embedded systems architectures, architectural explorations
and optimizations using different types of intellectual properties (IPs). The course defines the problems of architecture
allocation behavior, variable and channel partitioning and mapping,
selection of communications protocols, memory architectures, and estimation
of performance, power, and cost. The topics also include synthesis of
software and hardware for embedded systems and their relation to the
overall design process. The course also covers different types of models
necessary for the design process from specification to implementation and
CAD tools needed in the process.
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EECS222D System-on-Chip Hardware Synthesis
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 With
semiconductor technology advanced complex Systems-on-Chip (SoC) can be easily built today. However, our capability
to design such systems in reasonable time is not growing proportionally
with SoC complexity. This productivity gap is
forcing designers toward SW/HW codesign, higher
levels of abstractions and reusing predefined SW/HW blocks called
intellectual property (IPs). In this course
students will learn basic principles and techniques of system-level design
methodology for heterogeneous multiprocessor systems (MPSoCs)
and analyze each step of such a methodology in detail. The methodology will
start with an executable specification of the MPSoC
and will consider computational models, refinements and tools necessary to
convert the specification into a RTL design. The main emphasis will be on
generation and synthesis of components, to integrate such a multiprocessor
on a single chip. The students are required to have some background in
software or hardware engineering or both.
Text:
- Peter Marwedel, Embedded
Systems Design, Kluwer, 2003
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