PE Data Model characterizes the structure of PE and a memory sub-system. It consists of the following three data models: Datapath Model, Execution Model, and Memory Model.
Table 5-2. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
type | Name for type of processing element | User defined Identifier | String | User define |
Datapath model has a set of functional units and pipelines. It enumerates all the pipelines and functional units available in the PE. Multiple pipelines are allowed for superscalar architectures. This model is composed of a set of pipeline models and a set of functional unit models.
This model consists of type of a functional unit and its quantity in the PE. Delay for the functional unit is specified in operation model explained later.
Table 5-5. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
type | Name for type of functional unit | User defined Identifier | String | User define |
quantity | Number of the functional units available in the PE | ≥ 1 | Int | Data sheet |
Functional unit can operate in several modes. For each modes, it has different delays. For example, ALU may have addition and multiplication modes with different delays. In this model, delays for each operation modes are specified.
Pipeline model consists of a name and a set of pipeline stages. It also defines branch delay model which is a statistical model that stores the branch prediction policy, cycles lost for mis-prediction and the average mis-prediction ratio. Please note that current version of ESE does not use branch prediction policy for now. This attribute will be used when ESE supports a dynamic branch prediction model.
Table 5-9. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
name | Identifier for the pipeline | User defined Identifier | String | User define |
br_pred_policy | Branch prediction policy | TAKEN, NOT_TAKEN | String | User select |
br_penalty | Cycle lost for mis-prediction | Number of cycles | Int | Data sheet on PE |
br_pred_hit_ratio | Hit ratio from branch prediction | ≥0.00, ≤100.00 | FP | Simulation result by ISS or virtual platform |
Pipeline stage model has a set of pointers to a functional unit that is available in that pipeline stage. It consists of a set of pointers to functional unit model. Please note that we can describe non-pipelined datapath by defining only 1 stage inside of pipeline model. For this, please refer to the example of custom hardware in an Appendix B.
Table 5-11. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
name | Identifier for the pipeline stage | User defined Identifier | String | User define |
Pointer to functional unit model consists of type of functional unit and number of available functional units in the pipeline stage.
Execution model consists of a set of operation models and scheduling policy. Each operation model maps a operation to Datapath model and the scheduling policy decides the execution order for a given stream of operations.
Table 5-15. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
sched | Operation scheduling algorithm used by the PE such as ASAP, ALAP, List scheduling etc. | PIPELINE, LIST_SCHED | String | User select |
This model consists of the LLVM operations and their mapping to a pipelined datapath as defined in Datapath model. Please note that operation model uses LLVM operations instead of the specific set instruction sets or operations to make estimation framework re-targettable. LLVM operations can be easily mapped to the operations or instructions supported by the PE. To give an example, 'add', 'addc', 'addk' and 'addkc' instructions in the instruction set of MicroBlaze can be mapped to 'add' operation in LLVM instruction set. One LLVM operation can take care of several data types. Therefore, data type of variable for the operation should be also specified. Unless data type for the operation is not specified, no input or integer type is assumed.
The mapping of LLVM operation to a pipelined datapath consists of two steps. The first step is to map an operation to a set of pipeline stages and the second is to map available functional units to the pipeline stage. This mapping is done by two references, pipeline stage reference and functional unit reference explained later.
Table 5-17. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
name | Name of LLVM instruction | LLVM instruction | String | A set of LLVM instruction |
var_type | Type of operand for LLVM instruction | int, float, double | String | User select |
The pipeline stage reference consists of two flags and a pointer to a pipeline stage defined in Datapath model. Two flags are 'demand operand' and 'commit result' that specify the pipeline stages where the operation needs operand and commits the result, respectively.
Table 5-19. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
name | Pointer to a pipeline stage | Name of a pipeline stage | String | Datapath model |
flags | Specify 'demand operand' and 'commit result' | 'COMMIT', 'DEMAND' 'COMMIT DEMAND' | String | User select |
Functional unit reference is used to associate a pipeline stage with functional units used by operation in the pipeline stage. It specifies a type of functional unit along with its operation mode.
Memory model defines cache model and external memory model. Current version of ESE can support one level cache in a memory sub-system.
Current cache model is a statistical model. The model specifies cache policy and its delay for an instruction cache and a data cache. It also defines average cache hit ratio for a set of cache sizes. Please note that cache policy is not used in current version of ESE now. This attribute will be used when ESE supports a dynamic cache model.
Table 5-24. Attribute
Name | Description | Value | Type | Source |
---|---|---|---|---|
policy | Cache policy | D-Mapped, 2way-Set | String | User select |
i_cache_delay | Delay for an instruction cache | Number of cycles | Int | Data sheet |
d_cache_delay | Delay for an data cache | Number of cycles | Int | Data sheet |
Instruction cache model defines cache hit ratio for a cache size.
Data cache model defines cache hit ratio for a cache size.
The external memory latencies for memory read and memory write are specified here.