4.4. Generating Functional and Timed TLMs

The previous steps complete the platform and application input that is necessary for generation of TLMs. We will show generation of two types of SystemC TLMs. The first one is called the "Functional TLM" because it is used for the validation of design functionality only. It is completely un-timed and simulates the design based on causal dependency only. A universal bus channel is used to model the system bus and the mapping of channels on the bus.

The second TLM is called the "Timed TLM" and is used for performance estimation of the design. It relies on timing data models of PEs and Buses that are available in the ESE database. The data models are used by our estimation and annotation technique to apply "wait" statements in the application C code. The technique is retargetable and applicable to processors as well as HW IPs. A retargetable bus timing annotation modifies the bus channel to apply "wait" statements for inter-PE communication.

4.4.1. Generate Functional TLM

After the platform and application input is complete, the functional TLM can be generated automatically by selecting Synthesis->Generate Functional TLM from the menu bar. This will generate the SystemC code needed for platform modeling, including PEs, buses and transducers. The generated code is then compiled natively along with the C application code and linked to the SystemC libraries to produce a single binary. This process can be viewed in the log window.

4.4.2. Simulate Functional TLM

Once the compilation has completed, the generated TLM can be executed from the GUI by selecting Validation->Simulate Functional TLM from the menu bar.

4.4.3. View Functional Simulation Results

The simulation pops up a terminal that shows the picture size of BMP input that have been encoded. The JPEG encoder we are using deals with BMP inputs of 640x480 size. An additional window shows the picture of the encoded JPEG which is the output of the simulation. The pop up windows can now be killed simply by pressing "Enter" in the simulation logging terminal.

4.4.4. Generate Timed TLM

Similar to the functional TLM generation, the Timed TLM can be generated automatically by selecting Synthesis->Generate Timed TLM from the menu bar. The bus channels generated for timed TLM will include timing for synchronization, arbitration and data transfer. The timing parameters are imported into the TLM from the bus data model. For the computation part, we use a retargetable source level timing estimation technique that utilizes the PE data models. Naturally, the timed TLM generation and compilation is significantly slower than functional TLM generation, but still in the order of seconds.

4.4.5. Simulate Timed TLM

To simulate the generated timed TLM, simply select Validation->Simulate Timed TLM from the menu bar, after the TLM compilation has ended.

4.4.6. View Timed Simulation

The timed TLM simulation looks very similar to the functional TLM simulation except for one marked difference. Notice that timed simulation is significantly slower than functional TLM simulation. This is natural since we are simulation a lot more "wait" statements that are annotated to the application codes. However, our results show that this is still several orders of magnitude faster than RTL simulation for the same design.

When the timed simulation ends, several statistical data are dumped in the simulation logging terminal. These are the estimated cycles for CPU computation and communication, bus congestion estimates and so on. However, all these estimated performance statistics can be viewed graphically as shown in next section.