The bus model defines the available features and delays that distinguish each protocol.
Table 5-31. Attribute
Name | Description | Value | Type |
---|---|---|---|
type | Bus protocol identifier | Name of a functional unit | String |
address_bus_width | Width of the address bus | Width in bits | Integer |
data_bus_width | Width of the data bus | Width in bits | Integer |
max_number_masters | Maximum number of masters the bus allows | Number of masters | Integer |
fcfs | First Come First Served arbitration policy | TRUE, FALSE | Bool |
round_robin | Round Robin arbitration policy | TRUE, FALSE | Bool |
priority | Priority arbitration policy | TRUE, FALSE | Bool |
least_freq_used | Least Frequently Used arbitration policy | TRUE, FALSE | Bool |
arbitration_pipelining | Support for Arbitration pipelined with Address phase | TRUE, FALSE | Bool |
arb_req_delay | Arbitration Request delay | ≥1 | Integer |
default_master | If a PE is a default master (bus parking) | TRUE, FALSE | Bool |
split_transactions | Support for Split transactions | TRUE, FALSE | Bool |
retry | Support for RETRY operations | TRUE, FALSE | Bool |
retry_cycles | Number of cycles before a PE retries | ≥1 | Integer |
timeout | Support for Timeout if a PE does not respond | TRUE, FALSE | Bool |
timeout_cycles | Number of cycles before a Timeout is called | ≥1 | Integer |
preemption | Support for process preemption | TRUE, FALSE | Bool |
master_abort | Support for Abort | TRUE, FALSE | Bool |
bus_lock | Support for locking a bus to a PE | TRUE, FALSE | Bool |
burst_mode | Support for burst mode data transfer | TRUE, FALSE | Bool |
burst_mode_length | Length in cycles of the burst | ≥1 | Integer |
control_phase | Presence of a control phase before address/data phase | TRUE, FALSE | Bool |
control_phase_length | Length of the control phase in cycles | ≥1 | Integer |
address_data_pipelining | Support for pipelining between address and data phases | TRUE, FALSE | Bool |