5.2. Bus Model

The bus model defines the available features and delays that distinguish each protocol.

Table 5-31. Attribute

NameDescriptionValueType
typeBus protocol identifierName of a functional unitString
address_bus_widthWidth of the address busWidth in bitsInteger
data_bus_widthWidth of the data busWidth in bitsInteger
max_number_mastersMaximum number of masters the bus allowsNumber of mastersInteger
fcfsFirst Come First Served arbitration policyTRUE, FALSEBool
round_robinRound Robin arbitration policyTRUE, FALSEBool
priorityPriority arbitration policyTRUE, FALSEBool
least_freq_usedLeast Frequently Used arbitration policyTRUE, FALSEBool
arbitration_pipeliningSupport for Arbitration pipelined with Address phaseTRUE, FALSEBool
arb_req_delayArbitration Request delay≥1Integer
default_masterIf a PE is a default master (bus parking)TRUE, FALSEBool
split_transactionsSupport for Split transactionsTRUE, FALSEBool
retrySupport for RETRY operationsTRUE, FALSEBool
retry_cyclesNumber of cycles before a PE retries≥1Integer
timeoutSupport for Timeout if a PE does not respondTRUE, FALSEBool
timeout_cyclesNumber of cycles before a Timeout is called≥1Integer
preemptionSupport for process preemptionTRUE, FALSEBool
master_abortSupport for AbortTRUE, FALSEBool
bus_lockSupport for locking a bus to a PETRUE, FALSEBool
burst_modeSupport for burst mode data transferTRUE, FALSEBool
burst_mode_lengthLength in cycles of the burst≥1Integer
control_phasePresence of a control phase before address/data phaseTRUE, FALSEBool
control_phase_lengthLength of the control phase in cycles≥1Integer
address_data_pipeliningSupport for pipelining between address and data phasesTRUE, FALSEBool