In this tutorial we presented the ESE Front-End design methodology and tool set. ESE produces two types of TLMs; one for untimed functional verification and a timed TLM for performance estimation. The C/C++ and graphical input not only allows non-experts to create system models, but it also supports reuse of legacy code for product upgrades. The TLMs generated by ESE Front-End can be synthesized into board prototype models by ESE Back-End. This feature is not available in any commercial or academic offering.
To draw the conclusion, ESE enables embedded system developers to use the following powerful advantages that have never been available before.
Automatic TLM generation.
New TLMs are generated automatically from a mapping of C/C++ application to an abstract graphical platform. This means that the designer may use existing application code and map it to different platforms without having to manually modify any SystemC code.
Eliminates SLDL learning.
ESE eliminates the need for system-level design languages to be learnt by the designer. Only the knowledge of C for creating application specification is required.
Enables non-experts to design.
This also enables non-experts to design systems. There is no need for the designer to worry about design details like protocol timing diagrams, low level interfaces etc. Consequently, software developers can design systems.
Supports platforms.
ESE is great for platform based design . System platforms can be graphically created and modified. Pre-existing platforms can be reused and upgraded. All of these tasks are orthogonal to the application development itself.
Customized methodology.
ESE can also be customized to any methodology as per the designer's choice of components, system architecture, models and levels of abstraction.
Enables IP reuse.
ESE simplifies IP reuse to a great extent by allowing import of RTL components at system level. With C models of the IP, the designer can generate high speed TLMs for verification and performance estimation.
Supports interoperability.
ESE supports interoperability with industry standard languages and tools . The input is C/C++ which is the language of choice for embedded applications. The output is SystemC which is the de-facto system level design language. The Back-End in ESE allows generation RTL blocks from C code using third party high level synthesis tools, such as Forte. The final output of ESE Back-End is a Xilinx project that can be input to the Xilinx Embedded Development Kit (EDK) for push button FPGA prototyping.