The basic purpose of this tutorial is to guide a user through our Embedded System Environment (ESE) Front End. ESE helps designers to take C/C++ application processes and graphical platform capture and automatically produce Transaction Level Models (TLMs) for functional verification and performance estimation. Extensive information about ESE and its projected impact on embedded system design processes is available on our website at htt://www.cecs.uci.edu/~ese
The tutorial demostrates ESE Front End being used for TLM generation using the JPEG encoder and MP3 decoder applications. Three platforms are used for this purpose. The first platform consists of five microprocessors connected via a shared bus and communicating each other using a memory architecture. This platform is representative of a multi-processor design where all components are programmable. The second platform demonstrates usage of ESE for heterogeneous system design with one microprocessor and four HW accelerators. The HW Intellectual Properties (IPs) have a proprietary bus protocol which requires a protocol convertor between the processor bus and IP bus. The last platforms has two multi-threaded microprocessors to which several processes are mapped, thus it needs a Real-Time Operating System (RTOS) model to control the execution of the processes in a microprocessor. The design examples show the versatility of ESE, which is a huge benefit over manually written virtual platforms.
The tutorial gives a step by step illustration of using ESE Front End. Screenshots of the Graphical User Interface (GUI) are presented to aid the user in using the various features of ESE. Please note that, depending on your specific version of ESE and your system settings, the screen shots shown in this document may be slightly different from the actual display on your screen. The screenshots at each design step are supplemented with brief observations about the specific ESE feature. This would help the designer to gain an insight into the design process instead of merely following the demostration steps. We wind up the tutorial with a conclusion and references.
The rise in complexity of modern design has forced system designers to move to higher levels of abstraction above Register Transfer Level (RTL) and traditional cycle accurate design. Therefore, models such as TLMs that provide manyfold speedup over RTL simulation are being used. However, in order for TLMs to be synthesizable to Hardware (HW) and Software (SW) implementation, they must follow well defined semantics. These semantics are currently missing in the industry and TLM standards. Moreover, enforcing semantics is not easy with manual modeling.
Secondly, embedded application developers come from a variety of different engineering backgrounds and are not necessarily adept at electronic deign. Model automation tools are needed for such developers so that they do not need to learn modeling languages such as SystemC.
Thirdly, businesses that use external suppliers for their embedded system designs need unabmiguous executable specifications for design hand-off. An even better proposition would be to build pre-silicon board prototypes in house. This would reduce the chances for mis-communication in requirement specification and lead to a more robust design process. Consequently, tools are required that take abstract applications and platforms and quikcly produce fast TLMs and board prototypes.
It is with these challenges in mind that we have come up with ESE that takes off the drudgery of manual modeling from system designers. It enables non-experts to create system models and generate board prototypes using a convenient graphical interface.
To demonstrate the usefulness of ESE, two applications were chosen, JPEG encoder and MP3 decoder. JPEG encoder is used to demonstrate multiprocessor system design and system design including RTOS with ESE. MP3 decoder is used to demonstrate heterogeneous system design with ESE.
shows the block diagram of JPEG encoder. It takes a BMP as an input and outputs an encoded JPEG file. In general, JPEG encoder consists of five processes. First, it partitions the image into 8x8 blocks of pixels and the blocks are applied to a 2-dimensional DCT. Next, the transform matrix is normalized by an 8x8 quantization matrix and the quantized DCT coefficients form a matrix. The elements of the matrix are ordered in a zigzag scan. Then, an entropy coder combined with a run-length coding of the zeros generates an efficient representation of the quantized coefficients to be transmitted or stored. The C model is used to create test benches with golden JPEG output files. These test benches are used later to verify the ESE generated TLMs.
MP3 decoder first reads a codeword via synchronous and error checker. Next, huffman decoder translates the codeword to several symbols using variable length decoding algorithm and sends it to next stages for requantizing and reordering. Then, the decoded frequency line is sent to alias reduction and IMDCT. Finally, DCT produces the output samples. The block diagram in shows the IMDCT and DCT transforms that are applied during the stereo decoding on the left and right channels of the MP3 input. These function blocks are the most time consuming part of the decoding and are hence ideal for implementation using custom HW for faster decoding. The C model is also used to create test benches with golden PCM output files. These test benches are used later to verify the ESE generated TLMs.