Embedded System Environment (Front End): ESE Version 2.0 evaluation; Tutorial | ||
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We will start by loading the design of the JPEG encoder into ESE. As mentioned earlier, we will start with a partial platform consisting of one multi-threaded Microblaze processor and one OPB. The processor carries the application code for three processes in the JPEG encoder. One Microblaze processor for "zigzag" and "huffencode" processes will be added to the platform and then the two processes will be multi-threaded by adding a RTOS model. In this section, we will show how to use the database and platform editor canvas and how to upgrade a platform in ESE.
We begin by adding the already created partial design. The ESE designs are stored in XML based files with the extension ".eds." Select File->Open from the menu bar. Browse into the demo working directory and select "jpeg_mtd_platform_partial.eds." This is the design with the partial design example including RTOS. Press Open to open the design.
The partial platform will appear in the canvas as shown in the above screenshot. We can see one multi-threaded Microblaze processors CPU0 in the platform. The processor is connected via the Open Peripheral Bus (OPB). There are two local FIFO channels in this partial design. Each process has its own process port and the process port is connected through the FIFO channel. For example, as shown in PE window, CPU0 has three processes, "readbmp", "chendct" and "huffencode". Among them, the "readbmp" process has a process port which is for sending data from "readbmp" to "chendct". And the process port is connected to a local FIFO channel named "r2c" as shown at the bottom in PE window. Since this channel is for the intra-process communication in a processor, the channel is located to a local memory and is shown in the PE window not the Channel window which only shows the channels for the inter-process communication. Note that the processor is both connected as "Master" as indicated by an "M" at the connecting port. Since bus master cannot communicate directly over the bus, we provide a transducer (Tx0) which consists of a FIFO controller and FIFO memories. It acts as a shared memory for data transfer between CPU0 and CPU1.
Adding a new PE to the platform is very easy. Browse the database under the Processing tab and select Microblaze. Now drag and drop the selection into the platform canvas. The new PE of type "Microblaze" will be added to the platform!.
After the drag-drop, the user will find the new PE called PE0 in the platform. This is the PE that will host the "zigzag" and "huffencode" processes in the design. We start by providing an appropriate name to the new PE to be consisten with the rest of the design. To do so, right click on the PE0 box and select Properties.
In the properties dialog, change the PE name of the PE0 to "CPU1" to be consistent with the other PE names.
The new PEs, CPU1 is not yet connected to the rest of the design. Since the application processes meant to execute on the PE will need communication with processes on other processor, we must physically connect CPU1 to the shared OPB bus in the platform. For this physical connection, a port is required for CPU1. To add the port, simply right-click on the CPU1 box and select Add Port.
The created port must be connected to the OPB bus to be able to communicate with the rest of the system. Note that CPU1 is Microblaze core. This means that it can only connect to the OPB bus as a Master. To connect CPU1, right-click on the port and select Connect To->OPB0->M from the menu choice. This will create the bus connection and complete the platform design step. Next, we will look at application input and its mapping to the created platform.