Design Quality
Design Time Savings
Verification Time Savings
ESE Back-end Features
Graphical
TLM capture
with application C code and platform specification.
Automatic system SW generation
for each processor.
Cycle accurate RTL
synthesis or IP import for all HW cores.
Automatic interface generation
for protocol translation between incompatible cores.
FPGA/ASIC-ready PCAM output
with synthesizable RTL for all HW and drivers with application C code for downloading to embedded processors.
Designer Advantages
Graphical entry of TLM:
No need to learn system level modeling style or languages
Automatic RTL generation:
No need to develop synthesizable RTL code for HW interfaces
Automatic SW generation:
No need to develop processor and platform specific system SW
TLM is easier to debug and fix:
No need to simulate, learn and debug cycle accurate models
Management Benefits
Models are automatically generated:
1000x productivity gain, shorter time to market
Design decisions and models can be exchanged:
Simplified globally-distributed collaboration
Designs can be easily modified and prototyped:
Better market penetration through customization
Models and design decisions can be reused:
Easier derivatives and version management
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