PhD Final Defense
by Lochi Yu
Title: Automatic Generation and Verification of Transaction Level Models
Location: ET 331
Date and Time: June 18, 2009 10:00am
Committee:
Professor Daniel Gajski (Chair)
Professor Rainer Doemer
Professor Ian Harris
Abstract:
The rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless, several drawbacks exist: TLMs are fast, but their accuracy is low, TLMs are being coded manually, often by the use of a System Level Design Language (SLDL), there is no widely-adopted and tool-supported TLM style, and there has been little work on verifi cation at the System Level. In this dissertation, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA...
view full abstract
|
PhD Final Defense
by Hansu Cho
Title: Transducer Synthesis for Heterogeneous Multi-processor Systems
Location: EH 2210
Date and Time: July 9, 2009 8:30am
Committee:
Professor Daniel Gajski (Chair)
Professor Rainer Doemer
Professor Ian Harris
Abstract:
Contemporary system design requires more computational power than ever. To overcome this problem, MPSoC is widely used, but design complexity have been increased rapidly. Meanwhile, short time to market forced system designer to reduce development time. Therefore, designer raised the level of abstraction into the higher level called transaction level. But, current high level synthesis tools are dedicated to computational components only. To our best knowledge, there is no synthesis tool for communication components from the transaction level model down to RTL model. In this dissertation, we present a component called transducer which can handle heterogeneous MPSoC communication with multiple buses. Also, we presents a tool for automatic synthesis of transducer. The tool captures the communication parameters in the platform at transaction level and generates transducer in RTL. The design and configuration of the transducer depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the transducer can be automatically derived based on these parameters...
view full abstract
|
