Four different general tool sets can be envisioned around the SoC methodology, forming SoC system-level design flows with varying degrees of interactivity, automation and complexity.

At the core of the SoC methodology are four models at four levels of abstraction from specification down to implementation. Therefore, the first part of the SoC design flow is a simple modeling engine that allows the designer to compile, simulate and refine the four SoC models. The compilation and simulation of models are automatic. However, the designer is required to refine the models manually, following the refinement rules. The equivalence of original and refined models can be demonstrated through simulation and validation.

The refinement engine allows designers to automatically refine the models by making decisions through the refinement user interface (RUI) and using refinement tools. In this case, the designer is required to write only one model: the specification model, which is the easiest one to write since it is void of any implementation details. This model becomes the golden model, and all other models are derived from it. The specification model, with all design decisions stored, represents the complete synthesis flow and can be repeated anytime, anywhere or modified for different markets or different technologies.

The exploration engine incorporates additional profiling and estimation tools to allow designers to make better decisions. The tools must be accompanied by databases with proper component and protocol models needed for estimation of different metrics. On the other hand, if models are not available, the designers can write those models themselves. Most of the models can be represented by tables that designers must compile for insertion of a new component into the database.

The synthesis engine includes synthesis tools for architecture, communication and implementation. All or any number of synthesis tools can be included. For example, if the architecture is fixed, such as in a platform design, the architecture synthesis tool can be omitted. Similarly, if only a standard bus is used, the communication synthesis is not required. Furthermore, if no custom hardware is needed, the implementation synthesis can be substantially simplified.