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Within SoC Design Environment (SCE), starting from an initial system specification, an implementation of the system is created through a series of interactive and automated steps by gradually synthesizing and assembling a system design using components taken out of a set of databases.

SCE uses four models to reect design decisions during system-level synthesis: specification model, architecture model, network model and communication model. The communication model can be pin-accurate or transaction-level model. This report denes and describes pin-accurate communication model required for system-on-chip (SoC) design.

Generally, pin-accurate communication models need to represent processing elements (PEs), memories, communication elements (CEs) and bus wires connecting components. In this report we aim to provide an exhaustive list of requirements for pin-accurate communication in an automated SoC design flow using the example of concrete models. Specifically, the communication model in this report is used successfully in our SCE.

Within SoC Design Environment (SCE), starting from an initial system specification, an implementation of the system is created through a series of interactive and automated steps by gradually synthesizing and assembling a system design using components taken out of a set of databases.

SCE uses four models to reect design decisions during system-level synthesis: specification mode, architecture model, network model and communication model. The communication model can be pin-accurate or transaction-level model. This report denes and describes transaction-level communication model (TLM) required for system-on-chip (SoC) design.

Generally, TLMs need to represent processing elements (PEs), memories, communication elements (CEs) and protocol channels connecting components. In this report we aim to provide an exhaustive list of requirements for transaction-level modeling in an automated SoC design flow using the example of concrete models. Specifically, the communication model in this report is used successfully in SCE.

The SCE system-level design flow consists of a series of refinement steps that gradually transform an abstract specification model into an architecture model, a network model, a communication model and finally a detailed implementation model. The transformations can be automated with model refinement tools.

This report describes the styles of network models automatically generated by the network refinement tool. Therefore it can help designers understand the network models. It can also be used as a reference maunal if designers want to write their own network models that are valid input to the communication refinement tool.

The SCE system-level design flow consists of a series of refinement steps that gradually transform an abstract specification model into an architecture model, a network model, a communication model and finally a detailed implementation model. The transformations can be automated with model refinement tools.

This report describes the styles of architecture models automatically generated by the architecture refinement tool. Therefore it can help designers understand the architecture models. It can also be used as a reference maunal if designers want to write their own architecture models that are valid input to the network refinement tool.

Despite extensive research efforts for a number of years, modeling of RTL designs has still not reached a satisfactory state. Behavioral RTL design models still lack cycle-accuracy when multi-cycle and/or pipelined components are used. With such components, cycle-accuracy is only reached at the end of the RTL design flow when a complex structural netlist is obtained. Observation, debugging and modification efforts, however, are very tedius and difficult in such a model due its complexity.

This report provides a simple yet powerful solution to this problem. An easy-to-understand RTL model is proposed that supports clock-cycle accuracy in a behavioral description even in the presence of multi-cycled and/or pipelined components. Experiments show the effectiveness of the approach for specification, simulation, and synthesis.

Communication design for SoCs poses the unique challenges in order to cover a wide range of architectures while offering new opportunities for optimizations based on the application specific nature of system designs. In this report, we propose automatic generation of communication architecture from communication link model where system components communicate through logical links of network architecture. Automatic model refinement for communication architecture enables rapid design space exploration in order to achieve the required productivity gains. The experimental results show the benefits of our methodology and demonstrate the effectiveness of our automatic model generation for communication design.

Communication design for SoCs poses the unique challenges in order to cover a wide range of architectures while offering new opportunities for optimizations based on the application specific nature of system designs. In this report, we propose automatic generation of communication topology from partitioned, scheduled architecture model where system components communicate through message passing channels. Automatic model refinement for network topology enables rapid design space exploration in order to achieve the required productivity gains. The experimental results show the benefits of our methodology and demonstrate the effectiveness of our automatic model generation for communication design.

Fast and accurate estimation is critical for exploration of any design space in general. As we move to higher levels of abstraction, estimation of complete system designs at each level of abstraction is needed. Estimation should provide a variety of useful metrics relevant to design tasks in different domains and at each stage in the design process.

In this report, we present such a system-level estimation approach based on a novel combination of dynamic profiling and static retargeting. Co-estimation of complete system implementations is fast while accurately reflecting even dynamic effects. Furthermore, retargetable profiling is supported at multiple levels of abstraction, providing multiple design quality metrics at each level. Experimental results show the applicability of the approach for efficient design space exploration.