UCI Cadlab Technical Reports 2002 ---------------------- < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> < --> Disclaimer -- Permission to make digital/hard copy of all or part of any of the following publications and technical reports for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission. [pdf-icon.gif] [TR-02-33] Daniel D. Gajski, "System Level Design Flow: What is needed and what is not," CECS, UC Irvine, Technical Report CECS-TR-02-33, November 2002. [pdf-icon.gif] [TR-02-32] Lukai Cai, Daniel D. Gajski, "Variable Mapping of System Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-32, October 2002. This report presents a variable-memory mapping approach of the system level design, which maps the variables of the system behavior to the memories of the system architecture. It first introduces a novel memory size model to compute the required minimal memory sizes when allowing variables with un-overlapped lifetime to share the same memory portion. It then presents variable mapping algorithms for different design assumptions. The variable mapping algorithms are applied before obtaining some implementation details, such as bus topology and bus protocols, which moves the variable mapping to the earliest design stage. [pdf-icon.gif] [TR-02-31] Lukai Cai, Daniel D. Gajski, "Grouping-Based Architecture Exploration of System-Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-31, August 2002. This report introduces the grouping-based architecture exploration of the system level design. The grouping-based architecture exploration selects processing elements (PEs) to assemble the system architecture according to the design's functionality. Furthermore, it maps designs functional blocks to the selected PEs to pursue the shortest execution time . This report outlines the design flow of the grouping-based architecture exploration and describes a list-scheduling based algorithm for the grouping-based architecture exploration. [pdf-icon.gif] [TR-02-30] Lukai Cai, Daniel D. Gajski, Mike Olivarez, Paul Kritzinger, "C/C++ Based System Design Flow Using SpecC, VCC and SystemC," CECS, UC Irvine, Technical Report CECS-TR-02-30, June 2002. This report presents a C/C++ based system design flow that uses SpecC, VCC and SystemC tools. The design starts with a pure C model that is then converted into a SpecC model. A so-called behavior exploration task then takes place to analyze and optimize the system behavior. We then perform architectural exploration using VCC. Once this is complete, the behavior model is refined to an architecture model utilizing the SpecC methodology and the SpecC refinement tool. Finally, the design is linked to implementation using SystemC. We utilize this design flow to achieve the design from C to silicon in an efficient manner. An example of the JPEG encoder is utilized to prove this methodology. [pdf-icon.gif] [TR-02-28] S. Abdi, J. Peng, R. Dömer, D. Shin, A. Gerstlauer, A. Gluhak, L.Cai, Q. Xie, H. Yu, P. Zhang, D. Gajski, "System-On-Chip Environment (SCE): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-02-28, September 2002. [pdf-icon.gif] [TR-02-25] Haobo Yu, Daniel D. Gajski, "RTOS Modeling in System Level Synthesis," CECS, UC Irvine, Technical Report CECS-TR-02-25, August 2002. System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level synthesis for early design exploration. While real time operating systems (RTOS) are an increasingly important component in system design, specific RTOS implementations can not be used directly in high level models. On the other hand, existing system level design languages (SLDL) lack support for RTOS modeling. In this paper we propose a RTOS model built on top of existing SLDLs which, by providing the key features typically available in any RTOS, allows the designer to model the dynamic behavior of multi-tasking systems at higher abstraction levels to be incorporated into existing design flows. Experimental result shows that our RTOS model is easy to use and efficient while being able to provide accurate results. [pdf-icon.gif] [TR-02-20] Lukai Cai, Daniel D. Gajski, "Specification Tuning of System-Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-20, June 2002. This report presents the specification tuning of system-level design. Specification tuning changes the specification representing the design's functionality in the system level thus making the specification suitable for architectural exploration. We introduce parallelization optimization and hierarchy reducing, the two main tasks of specification tuning. In addition, we also introduce two tools, spec profiler and spec optimizer, to implement these tasks automatically. [pdf-icon.gif] [TR-02-18] Lukai Cai, Daniel D. Gajski, "Parallelization Optimization of System-Level Specification," CECS, UC Irvine, Technical Report CECS-TR-02-18, June 2002. This paper introduces the parallelization optimization of system-level specification, which explores maximal parallelism among functional blocks of the design. We introduce two tools, spec profiler and spec optimizer, to implement the parallelization optimization automatically. [pdf-icon.gif] [TR-02-17] Andreas Gerstlauer, Daniel D. Gajski, "System-Level Abstraction Semantics," CECS, UC Irvine, Technical Report CECS-TR-02-17, July 2002. Raising the level of abstraction is widely seen as the solution for closing the productivity gap in system design. They key for the success of this approach, however, are well-defined abstraction levels and models. In this paper, we present such system level semantics to cover the system design process. We define properties and features of each model. Formalization of the flow enables design automation for synthesis and verification to achieve the required productivity gains. Through customization, the semantics allow creation of specific design methodologies. We applied the concepts to system languages SystemC and SpecC. Using the example of a JPEG encoder, we will demonstrate the feasibility and effectiveness of the approach. [pdf-icon.gif] [TR-02-16] Andreas Gerstlauer, "SpecC Modeling Guidelines," CECS, UC Irvine, Technical Report CECS-TR-02-16, April 2002. Raising the level of abstraction to the system level has been touted as the main solution for closing the productivity gap designers of embedded systems-on-chip (SOCs) are facing increasingly. However, in order to achieve the required productivity gains, a well-defined methodology enabling a synthesis-oriented flow is necessary. The basis for every methodology are clear and unambiguous models at different levels of abstraction. In this report, we will define the four models that comprise the SpecC system-level design methodology. Using actual code templates, we will show their features and properties in detail. All together, this report provides comprehensive guidelines for modeling a design at each level. In addition to standardizing manually written models, the exact definition of the models builds the basis of all automated tools for exploration, refinement, synthesis or verification. [pdf-icon.gif] [TR-02-15] Junyu Peng, Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, "Interactive System Design Flow," CECS, UC Irvine, Technical Report CECS-TR-02-15, April 2002. This report presents an interactive system design flow. The design tasks and scenarios are defined. Data displays and the design rules to use displays are discussed. The interactive design flow enables fast and extensive design exploration with minimal effort from designer's side. [pdf-icon.gif] [TR-02-14] Junyu Peng, Samar Abdi, Daniel D. Gajski, "Automatic Model Refinement for Fast Architecture Exploration," CECS, UC Irvine, Technical Report CECS-TR-02-14, April 2002. We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An architecture model is derived from the specification through a series of well defined steps in our design methodology. Traditional architecture exploration relies on manual refinement which is painfully time consuming and error prone. The automation of the refinement process provides a useful tool to the system designer to quickly evaluate several architectures in the design space and make the optimal choice. Experiments with the tool on a system design example show the robustness and usefulness of the refinement algorithm. [pdf-icon.gif] [TR-02-13] Dongwan Shin, Daniel D. Gajski, "Interface Synthesis from Protocol Specification," CECS, UC Irvine, Technical Report CECS-TR-02-13, April 2002. In system-on-chip design, automating design reuse is one of the most important issues. Since most Intellectual Properties(IP) are provided by different vendors, they have different interface schemes, and different data rates. In order to automate design reuse, methods for combining system components with incompatbile I/O and interface protocols, must be developed. Furthermore design interfaces between interacting components is an error-prone task. In this report, we propose the interface architecture in which queues are used for data transfers between components with incompatible protocols. We also describe a method to generate system interface from the protocol specification. [pdf-icon.gif] [TR-02-12] Dongwan Shin, Daniel D. Gajski, "Queue Generation Algorithm for Interface Synthesis," CECS, UC Irvine, Technical Report CECS-TR-02-12, February 2002. In system-on-a-chip design, automating design reuse is one of the most important issues. Since most Intellectual Properties(IP) are provided by different vendors, they have different interface schemes. In order to automate design reuse, methods for combining system components with incompatbile communication protocols must be developed because a large portion of integration is devoted to designing the interfaces between interacting components. In this report, we propose the interface architecture in which queues are used for data transfer between components with incompatible protocols and describe the algorithm for generating synthesizable RTL description of queues using arbitrary memories. [pdf-icon.gif] [TR-02-11] Dongwan Shin, Daniel D. Gajski, "Scheduling in RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-02-11, April 2002. In this report, we describe the novel RTL design methodology based on Accellera RTL semantics. We also propose the scheduling algorithm targeting bus-based architecture for the RTL design methodology. The proposed scheduling algorithm is based on resource constrained list scheduling, which considers the number of function units, storage units, buses and ports of storage units in each control step. It supports the pipelined/multicycle operations and storage units, such as pipelined register files and latched memory. [pdf-icon.gif] [TR-02-09] Pei Zhang, Daniel D. Gajski, "RTL Design and Synthesis of Sequential Matrix Multiplication," CECS, UC Irvine, Technical Report CECS-TR-02-09, April 2002. This report describes the RTL design and synthesis of Sequential Matrix Multiplication using accellera RTL methodology. We first begin with the introduction of Sequential Matrix Multiplication. Then we give the FSMD of Sequential Matrix Multiplication and critical path analysis to decide the clock cycle. Based on different resource constraint, the synthesis results (scheduling, storage binding, functional unit binding and interconnection binding) are given. The source codes are also included in the Appendix. [pdf-icon.gif] [TR-02-08] Lukai Cai, Daniel D. Gajski, "System Level Design Using SpecC Profiler," CECS, UC Irvine, Technical Report CECS-TR-02-08, April 2002. This report illustrates the use of SpecC profiler for the system level design at high levels of abstraction. SpecC profiler allows the designers to choose the granularity of specification, to select PEs for architecture, and finally to map specification to PEs based on the given design constraints. The report also provides system level design examples including JPEG encoder, JBIG encoder, and Vocoder projects. We show that the design processes are much smoother and easier with the use of SpecC profiler. [pdf-icon.gif] [TR-02-07] Lukai Cai, Daniel D. Gajski, "Introduction of Design-Oriented Profiler of SpecC Language," CECS, UC Irvine, Technical Report CECS-TR-02-07, March 2002. To start design from higher levels of abstraction and to make an architecture exploration decision at the early stage of design, designers must achieve the characteristics of specification on the higher levels of abstraction. Designers should also estimate the system performance at the higher levels of abstraction to ensure that the implemented system meets design constraints. In this report, SpecC profiler, a design-oriented profiler, accomplishes two tasks above, by evaluating the specification model of SpecC language. [pdf-icon.gif] [TR-02-06] Qiang Xie, Daniel D. Gajski, "Parity Checker Implementations in SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-06, January 2002. In this report we discuss an example where we synthesize a multiple implementations of a design with our RTL synthesis tool. We use different resource allocation combinations to obtain multiple implementations and perform synthesis on them. The initial part of this report introduces a Parity Checker, including its FSMD and implementation model. Then we further develop into different implementations of One's Counter. We do different combinations of allocation of different resources to the design and perform the synthesis on these implementations with our tool. We then analyze the performance of these implementations on the basis of synthesis results and show how the user has the choice to make the ultimate decision about the design with due considerations to all involved tradeoffs. [pdf-icon.gif] [TR-02-05] Haobo Yu, Daniel D. Gajski, "Datapath Synthesis for a 16-bit Microprocessor," CECS, UC Irvine, Technical Report CECS-TR-02-05, January 2002. In this report, well describe the datapath synthesis for a simple 16-bit microprocessor using our own RTL synthesis tool. The initial part of this report introduces the instruction set of the processor as well as its instruction set super FSMD model. Then we further develop into different implementations of the processor's datapath. We will try different resource allocation combinations to the design and perform the synthesis on different target RTL structure with our tool. We then analyze the performance of these implementations on the basis of synthesis results from our tool and show how the designer has the choice to make the ultimate decision about the design with due considerations to all involved tradeoffs. [pdf-icon.gif] [TR-02-04] Wolfgang Mueller, Rainer Dömer, Daniel D. Gajski, "The Formal Execution Semantics of SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-04, January 2002. We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, waitfor, par, pipe, and try statements as they are introduced in SpecC. We present our definition in form of distributed Abstract State Machine (ASM) rules reflecting the specification given in the SpecC Language Reference Manual. We mainly see our formal semantics in three application areas. First, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets. _________________________________________________________________ Last update: March 11, 2003 by A. Gerstlauer (gerstl@ics.uci.edu).