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Andreas Gerstlauer, Shuqing Zhao and Daniel D. Gajski,
"VHDL+/SpecC Comparisons - A Case Study,"
UC Irvine, Technical Report ICS-TR-98-23, May 1998.
In this report, we make a comparison between two system level design
languages - VHDL+ and SpecC - based on exploration of two worked examples
modeled in both languages. We introduce the main features of the two
language. Two examples, FIFO and FEC, are modeled with VHDL+ and SpecC. We
conclude with a comparison between these two languages.
En-Shou Chang and Daniel D. Gajski,
"System-Level Timing-constrained Scheduling,"
UC Irvine, Technical Report ICS-TR-98-15, January 1998.
Abstract HLS scheduling algorithms can not be applied on system-level
synthesis due to the following problems:
In this paper, we present a data-structure to specify the input
for system-level scheduling, and a system-level timing-constrained
scheduling algorithm. Static scheduling, which has no OS overhead and better
system WCET, is used. The algorithm presented can obtain near-optimal
solutions within acceptable and predictable CPU time.
- The control-step is not available at system-level.
- Mixed concurrent and exclusive execution flows.
- Synchronization among objects scheduled.
- Execution time of objects scheduled may not be determined until
Rainer Dömer, Jianwen Zhu, Daniel D. Gajski,
"The SpecC Language Reference Manual,"
UC Irvine, Technical Report ICS-TR-98-13, March 1998.
This Language Reference Manual defines the syntax and the semantics
of the SpecC language.
The SpecC language is an extension of the ANSI-C programming language.
Since ANSI-C is already well-documented, this report only describes the
special constructs that were added for SpecC.
For each SpecC construct, the syntax, the purpose and the semantics are
documented and an example is given for easy explanation. Also, the full SpecC
grammar is included using a formal notation in lex and yacc style.
Gaurav Aggarwal and Daniel D. Gajski,
"Exploring DCT Implementations,"
UC Irvine, Technical Report ICS-TR-98-10, March 1998.
The Discrete Cosine Transform (DCT) is used in the MPEG and JPEG
compression standards. Thus, the DCT component has stringent timing
requirements. The high performance which is required cannot be achieved
by a sequential implementation of the algorithm. In this report, we
explore different optimization techniques to improve the performance of
the DCT. We discuss various pipelining options to further reduce the
latency. We present a transformation of the algorithm that reduces the
memory requirements and hence, reduces the cost of the implementation.
We also describe RT-level implementations of the sequential, pipelined
and memory optimized designs.
Daniel D. Gajski, Gaurav Aggarwal, En-Shou Chang, Rainer Doemer,
Tadatoshi Ishii, Jon Kleinsmith and Jianwen Zhu,
"Methodology for Co-design of Embedded Systems,"
UC Irvine, Technical Report ICS-TR-98-07, March 1998.
In this report we describe a co-design methodology for design of embedded
systems. We describe the necessary design steps in order to map an abstract
specification of the system to the final implementation model. We propose a
co-design tool based on our co-design methodology. We also present a
graphical user interface for the proposed co-design tool.
Jon Kleinsmith and Daniel D. Gajski,
"Communication Synthesis for Reuse,"
UC Irvine, Technical Report ICS-TR-98-06, February 1998.
In this report we discuss a set of techniques needed to
generate and synthesize communication interfaces in a System Design
context. Given a behavioral specification, we present the
transformations necessary for generating a communication model
containing channels and protocol. This work is being conducted in
conjunction with codesign tools being developed in the CADLAB at the
University of California, Irvine.
Gaurav Aggarwal and Daniel D. Gajski,
"Modeling Guidelines for ASIC Reuse,"
UC Irvine, Technical Report ICS-TR-98-03, March 1998
In this report, we discuss the various issues and problems associated
with ASIC reuse. We describe the different models of communication
between components and the essential issues in interfacing ASICs that use
different communication protocols. We come up with guidelines that help in
modeling for reuse. We also propose a new HDL, SpecC, that has the
desirable characteristics for co-designing systems. This language is
suited for ASIC reuse and overcomes the limitations of VHDL.