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Identifying mutual exclusiveness between operators during behavioral synthesis is important in order to reduce the required number of control steps or hardware resources. The quality of the synthesized design is strongly influenced by the number of mutually exclusive operators that can be identified by synthesis algorithms. To improve the quality of the design, we propose a representation, the Condition Graph, and an algorithm for comprehensive identification of mutually exclusive operators. Previous research efforts have concentrated on identifying mutual exclusiveness by examining language constructs such as IF-THEN-ELSE statements. Thus, their results heavily depend on the description styles. The proposed approach can produce results independent of description styles and identify more mutually exclusive operators than any previous approaches. The Condition Graph and the proposed algorithm can be used in any scheduling or binding algorithms. Experimental results on several benchmarks have shown the efficiency of the proposed representation and algorithm.

The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. In this report, we motivate the need for such a standard RT component set, and describe a library environment that supports automatic model generation, design reuse, and synthesis with technology-specific estimators. We demonstrate the efficacy of the standard RT-component set approach with experiments performed on the HLSW92 benchmarks. Our preliminary results indicate only a small overhead of about 10% in using these standard, generic components. We then describe an automatic model generation and technology projection scheme that used fast (on-line) estimators for predicting the area and delay of generic RT components tuned to a particular technology library with an accuracy of 10%. These model generators and estimators have been integrated with a high-level synthesis system at U. C. Irvine.

Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath components during the tasks of scheduling and allocation. However, such datapath components are often custom designed and placed in technology libraries and databooks for potential reuse in future designs. We present a novel scheduling approach that, for the first time, permits reuse of such datapath components during HLS. Given a library of user-defined datapath components, an allocation of components from this library, and a limit on the maximum propagation delay through the datapath components, our algorithm generates an effective schedule for a given input behavior. We present experimental results of our approach on some HLS benchmarks using realistic combinatorial datapath components. Since the scheduling technique works on user-defined templates of datapath components and uses the delay information from the library for the components, we believe our approach can significantly impact design productivity through the reuse of complex RT datapath components.

We present High-level Library Mapping (HLLM), a technique that permits reuse of complex RT-level databook components (specifically ALUs). HLLM can be used to couple existing databook libraries, module generators and custom-designed components with the output of architectural or behavioral synthesis. In this report, we define the problem of high-level library mapping, present several algorithmic formulations for HLLM of ALUs, and demonstrate the versatility of our approach on a variety of libraries. We also compare HLLM against the traditional mapping approach using logic synthesis. Our experiments show that HLLM for ALUs outperforms logic-synthesis in area, delay and runtime, indicating that HLLM is a promising approach for reuse of datapath components in architectural design and high-level synthesis.

The use of a realistic component library with multiple implementations of operators results in cost efficient designs; slow components can then be used on non-critical paths and the more expensive components on only the critical paths. This report presents a cost-optimized algorithm for selecting components and pipelining a data flow graph, given a multiple-implementation library, and throughput and latency constraints. Results on several DSP examples indicate the importance of component selection as a parameter in design space exploration