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Existing heuristics and algorithms used in High-Level Synthesis typically assume a direct mapping of hardware description language (HDL) operators to RT units. This assumption simplifies synthesis but requires complex technology mapping to fully utilize the functionality of complex RT components. In this paper, we present an algorithm employing a novel representation scheme to more efficiently map abstract HDL behavior to realistic RT-component behavior. it enables efficient usage of complex databook components, custom designed cells, previously synthesized RT modules, and RT module generators. This approach can be used to customize HLS tools to user-specific RT libraries.

Partitioning a system's functionality among interacting hardware and software components is an important part of system design. We introduce a new partitioning algorithm that caters to the main objective of the hardware/software partitioning problem, i.e. minimizing hardware for given performance constraints. We demonstrate results superior to those of previously published algorithms intended for hardware/software partitioning.

We present a design exploration strategy for the beamformer system, an example of a typical DSP system. In order to do so, we first define a parameterized design template for the beamformer and for a FIR filter, since the filtering operation is a part of the overall beamformer system. We then discuss some approaches for varying the design parameters for the filter and the beamformer system, under constraints imposed by technology or the designer.

This document first gives a brief overview of the GENUS library of Generic Component Generators and describes the installation procedure for the library. It then presents the C-programming library interface and illustrates its use with some examples. The appendix has a complete list of the GENUS generators and some sample models.

VHDL and other hardware description languages have become popular as system specification languages in top-down design. However, their constructs do not support the behavioral specification of embedded systems. We introduce a new conceptual design model, called Program-State Machines, that caters to embedded systems. We then describe the SpecCharts language, an extended version of VHDL, which supports capture of this design model. In conjunction with a translator to VHDL, SpecCharts can be easily incorporated into a VHDL design environment, with the advantages of significantly reduced specification time and fewer errors. The extensions introduced for VHDL are applicable to many other hardware description languages as well. We demonstrate the advantages of using SpecCharts for system specification capture through several experiments.

In this report, we present an architectural classification based on four design features: customization, slicing direction, parallelism and pipelining. We also propose a strategy for exploring the architectural space of a design by varying these design features in a systematic way. We believe that design exploration carried out in such a manner will not only save considerable designer time and effort but also result in more cost-effective designs. In order to demonstrate the effectiveness of our exploration strategy we give the results of applying it on four examples: a timer system, an FIR filter, an FFT datapath, and a robot kinematics system.

The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. Although no standard set of RT components seems to exist across different design methodologies and backend technologies, on closer examination, we see that there indeed does seem to be a universally accepted set of RT-components that are used in the initial phase of design refinement, much before its implementation in a particular target technology. In this report, we describe the need for such a standard RT component set, describe such a parameterized library of standard (or generic) RT components, and evaluate its utility in the system design process. We survey several backend technology libraries, and study the relative coverage of the generic RT component library with respect to these target technology libraries. We then describe the problem of high-level technology mapping, and illustrate this process for a few RT components. Finally, we perform a set of experiments on the HLSW92 benchmarks to evaluate the usefulness of generic RT component libraries. In particular, we compute the overhead incurred by using a generic RT component library over directly using the technology-specific components for the selected benchmark designs. Our preliminary results indicate that the penalty in using the generic components is quite low (approximately 10%), and is more than compensated by the advantages of designing with a generic RT component library.

This report contains transparencies of a presentation on the design process in the University of California Irvine's Behavioral-Synthesis Environment. The human-interface aspects of the environment are discussed in detail and several design-process examples are given to demonstrate the power and usefulness of this environment for behavioral synthesis.

Previous work in software/hardware codesign has addressed issues in system modeling, partitioning, and mixed module simulation and integration. Software estimation, which provides software metrics to assist the software/hardware partitioning, has not been studied. In order to rapidly explore large design space encountered in software/hardware systems, automatic software estimation is indispensable in software/hardware partitioning in which designers or partitioning tools must trade off a hardware with a software implementation for the whole or a part of the system under design. In this report we present a software estimator that provides three software metrics -- execution time, program-memory size and data-memory size for a specification executing on a given processor. Experiments have shown that our estimator has less than 20% estimation errors on different designs spanning from straight line code to code with branches and loops and even to hierarchical specifications. Experiments also show that our estimator is fast and can provide rapid feedback to the designers or partitioning tools to quickly evaluate different design alternatives.

This report describes a presentation on the design methodology and the user's view of the SpecSyn system design framework. Given an abstract specification of a system, we present specification capture and the subsequent refinements that will result in synthesizable descriptions. The advantages of the underlying methodology compared to current approaches are highlighted.