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RISC Compiler and Simulator, Release V0.6.0: Out-of-Order Parallel Simulatable SystemC Subset

Guantao Liu, Tim Schmidt, Zhongqi Cheng, Daniel Mendoza and Rainer Domer, “RISC Compiler and Simulator, Release V0.6.0: Out-of-Order Parallel Simulatable SystemC Subset“, CECS TR 19-04, posted on October 9, 2019