RISC Compiler and Simulator: Release Vo.4.0: Out-of-Order Parallel Simulatable SystemC Subset

Guantao Liu, Tim Schmidt, Zhongqi Cheng, Rainer Dömer, “RISC Compiler and Simulator, Release V0.4.0: Out-of-Order Parallel Simulatable SystemC Subset”, CECS TR 17-05, posted on July 31, 2017