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M. Reshadi and D. Gajski, "NISC Modeling and Compilation," TR 04-33, December 2004.
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A. Gupta and
R. Doemer, "System Design of Digital Camera Using SpecC," TR 04-32, December 10, 2004.
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R. Jejurikar and R. Gupta, "Leakage Aware
Dynamic Slack Reclamation in Real-Time," TR 04-31,
November 2004.
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pdf
A. Nacul and T. Givargis, "The Phantom Serializing
Compiler," TR 04-30,
November 22, 2004.
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pdf
S. Abdi and D. Gajski, "System Level Verification with Model Algebra," TR 04-29, November 9, 2004.
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M. Mamidipaka and N. Dutt, "eCACTI: An Enhanced Power Estimation Model for On-chip Caches," TR 04-28, September 14, 2004.
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S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, "Floorplan-aware Bus Architecture Synthesis," TR 04-27, October 2004.
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B. Gorjiara and N. Bagherzadeh, "Systematic Power Management of Heterogeneous Real-time Systems by Dynamic Schedule Analysis," TR 04-26,
August 2004.
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D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, "System-on-Chip Communication Modeling Style Guide," TR 04-25,
July 2004.
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D. Shin,
L. Cai,
A. Gerstlauer,
R. Doemer, D. Gajski, "System-on-Chip Transaction-Level Modeling Style Guide," TR 04-24,
July 2004.
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D. Shin, J. Peng,
A. Gerstlauer, R. Doemer, D. Gajski, "System-On-Chip Network Modeling Style Guide," TR 04-23,
July 31, 2004.
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J. Peng, A. Gerstlauer, R. Doemer, D. Gajski, "System-On-Chip Architecture Modeling Style Guide," TR 04-22, July 31, 2004.
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P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, P. Ienne, "ISEGEN: Adapting Kernighan-Lin Min-Cut Heuristic for Generation of Instruction Set Extensions," TR 04-21, August 12, 2004.
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S. Pasricha, N. Dutt, and M. Ben-Romdhane, " Automated Synthesis of Bus Architectures for Systems with Throughput Constraints," TR 04-20, August 2004.
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R. Doemer, A. Gerstlauer, D. Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," TR 04-19, July 22, 2004.
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S. Banerjee and N. Dutt, "Very Fast Simulated Annealing for HW-SW Partitioning," TR 04-18,
June 2004.
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P. Chandraiah, H. Schirner, N. Srinivas, and R. Doemer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder," TR 04-17, June 21, 2004.
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D. Shin, A. Gerstlauer, and D. Gajski, "Communication Link Synthesis for SoC," TR 04-16, June 10, 2004.
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D. Shin, A. Gerstlauer, and D. Gajski, "Network Synthesis for SoC," TR 04-15, June 10, 2004.
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R. Jejurikar and R. Gupta, "Systemwide Energy Minimization in Real-Time Embedded Systems," TR 04-14, May 2004.
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I. G. Harris, "On the Detection of Synchronization Errors," TR 04-13, May 2004.
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D. Gajski and M. Reshadi, "NISC Application and Advantages," TR 04-12, May 2004.
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S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Rapid Exploration of Bus-based Communication Architectures at the CCATB Abstraction," TR 04-11, May 2004.
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R. Jejurikar and R. Gupta, "Optimized Slowdown in Real-Time Task Systems," TR 04-10, April 2004.
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R. Jejurikar and R. Gupta, "Procrastination Scheduling in Fixed Priority Real-Time Systems," TR 04-09, April, 2004.
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M. Reshadi and D. Gajski, "NISC Modeling and Simulation," TR 04-08, March 2004.
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N. Savoiu,
S. Shukla, and R. Gupta, "A Semantics-Preserving Reduction of Code-Annotated Well-formed Free Choice Petri Nets," TR 04-07, February 12, 2004.
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S. Pasricha, M. Ben-Romdhane, and N. Dutt, "High Level Design Space Exploration of Shared Bus Communication Architectures," TR 04-06, March 13, 2004.
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P. Mishra and N. Dutt, "Functional Coverage Driven Test Generation for Validation of Pipelined Processors," TR 04-05, March 12, 2004.
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L. Cai, A. Gerstlauer, and D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," TR 04-04, February 2004.
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R. Jejurikar and R. Gupta, "Integrating Processor Slowdown and Preemption Threshold Scheduling for Energy Efficiency in Real Time Embedded Systems," TR 04-03, February 16, 2004.
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J. Trajkovic and A. Veidenbaum, "Reducing SDRAM Energy Consumption in Embedded Systems," TR 04-02, October 2004.
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R. Jejurikar and R. Gupta, "Energy Aware Non-preemptive Scheduling for Hard Real-Time Systems," TR 04-01, January 21, 2004.
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