B. Gorjiara, P. Chou, N. Bagherzadeh, "An Algorithm to Avoid Power Command Jitter in Middleware-Based Distributed Embedded Systems," TR 03-47, July 2003.
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B. Gorjiara, F. Kuester, P. Chou, and M. Reshadi, "GX-GUI: A General Extensible Technique for 2-D Interaction with VR Applications," TR 03-46, January 2003.
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L. Cai, A. Gerstlauer, S. Abdi, J. Peng, D. Shin, H. Yu, R. Doemer, D. Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Manual," TR 03-45, December 2003.
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D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "C-based Interactive RTL Design Methodology," TR 03-42, December 1, 2003.
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S. Abdi, J. Peng, H. Yu, D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "System-on-Chip Environment: SCE Version 2.2.0 Beta Tutorial," TR 03-41, December 2003.
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S. Banerjee and N. Dutt, "FIFO Power Optimization for On-Chip Networks," TR 03-40, December 19, 2003.
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N. Savoiu, S. Shukla, and R. Gupta, "Petri Net-based Thread Composition for Improved System Level Simulation," TR 03-39, December 29, 2003.
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A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt, and R. Gupta, "Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices," TR 03-38, November 2003.
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A. Nacul, S. Choudhuri, and T. Givargis, "POSIX-Compliant Portable Code Synthesis for Embedded Systems," TR 03-36, November 25, 2003.
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R. Jejurikar, C. Pereira, and R. Gupta, "Leakage Aware Dynamic Voltage Scaling for Real Time Embedded Systems," TR 03-35, November 30, 2003.
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A. Nacul and T. Givargis, "Dynamic Voltage and Cache Reconfiguration for Low Power," TR 03-34, November 7, 2003.
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D. Shin, S. Abdi, and D. Gajski, "Automatic Generation of Bus Functional Models from Transaction Level Models," TR 03-33, November 18, 2003.
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M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, "Leakage Power Estimation in SRAMs," TR 03-32, October 24, 2003.
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S. Abdi and D. Gajski, "System Debugging and Verification: A New Challenge," TR 03-31, October 1, 2003
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A. Gerstlauer, "Communication Abstractions for System-Level Design and Synthesis," TR 03-30, October 24, 2003.
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S. Abdi and D. Gajski, "Provably Correct Architecture Refinement," TR 03-29, September 30, 2003.
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D. Gajski, "NISC: The Ultimate Reconfigurable Component," TR 03-28, October 1, 2003.
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N. Bansal, S. Gupta, N. Dutt, A. N, and R. Gupta, "Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures," TR03-27, August 2003.
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A. Gerstlauer, L.Cai, D. Shin, R. Doemer, and D. Gajski, "System-On-Chip Component Models," TR 03-26, August 11, 2003.
Complete TR is available upon request

P. Mishra, N. Dutt and H. Tomiyama, "Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications," TR 03-25, July 28, 2003.
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S. Pasricha and A. Veidenbaum, "Novel Techniques to Improve Branch Prediction Accuracy for Embedded Processors in the Presence of Context Switches," TR 03-24, August 2003.
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Y. Agarwal and R. Gupta, "On Demand Paging Using Bluetooth Radios on
802.11 Based Networks," TR 03-22, June 2003.
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A. Gerstlauer, K. Ramineni, R. Doemer, and D. Gajski, "System-On-Chip Specification Style Guide," TR 03-21, June 25, 2003.
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M. Luthra, S. Gupta, N. Dutt. R. Gupta, A. Nicolau, "Interface Synthesis using Memory Mapping for an FPGA Platform," TR 03-20, June 25, 2003.
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R. Cornea, S. Mohapatra, N. Dutt, A. Nicolau, N. Venkatasubramanian, "Integrated Power Management for Video Streaming to Mobile Handheld Devices," TR 03-19, May 2003.
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H. Yu, R. Doemer, and D. Gajski, "Automatic Software Generation for System Level Design," TR 03-18, May 14, 2003.
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S. Pasricha, P. Biswas, P. Mishra, A. Shrivastava, A. Mandal, N. Dutt, and A. Nicolau, "A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor," TR 03-17, April 2003.
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P. Biswas and N. Dutt, "Greedy and Heuristic-based Algorithms for
Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs," TR 03-16, April 2003.
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C. Pereira, S. Gupta, K. Niyogi, I. Lazaridis, S. Mehrotra, and R. Gupta, "Energy Efficient Communication for Reliability and Quality Aware Sensor Networks," TR 03-15, April 21, 2003.
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S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, "Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow," TR 03-14, April 2003.
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D. D. Gajski and K. Ramineni, "C to SpecC Conversion Style," TR 03-13, April 4, 2003.
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D. D. Gajski, H. Yu, and A. Gerstlauer, "RTOS Scheduling in Transaction Level Models," TR 03-12, March 20, 2003.
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D. D. Gajski, L. Cai, and S. Verma, "Comparison of SpecC and SystemC Languages for System Design," TR 03-11, May 15, 2003.
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D. D. Gajski and L. Cai, "Transaction Level Modeling in System Level Design," TR 03-10, March 28, 2003.
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D. D. Gajski, A. Tripathi, and S. Verma, "G.729E Algorithm Optimization for ARM926EJ-S Processor," TR 03-09, March 21, 2003.
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D. D. Gajski and S. Abdi, "Automatic Communication Refinement for System Level Design," TR 03-08, March 7, 2003.
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R. Gupta, R. Jejurikar, and C. Periera, "Dual-Mode Frequency Inheritance Algorithm for Energy Aware Task Scheduling with Task Synchronization," TR 03-07, February 28, 2003.
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D. D. Gajski, S. Abdi, "Formal Verification of Specification Partitioning," TR 03-06, April 23, 2003.
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N. Dutt, M. Reshadi, P. Mishra, N. Bansal, "ReXsim: A Retargetable Framework for Instruction-Set Architecture Simulation," TR 03-05, February 10, 2003.
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N. Dutt, A. Kejariwal, P. Mishra, J. Astrom, "HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors," TR 03-04, February 3, 2003.
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D. D. Gajski and L. Cai, "Channel Mapping in System Level Design," TR 03-03, January 7, 2003.
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D. D. Gajski, J. Peng, A. Gerstlauer, H. Yu, and D. Shin, "System Design Methodology and Tools," TR 03-02, January 12, 2003.
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T. Givargis and A. Nacul, "Adaptive Online Cache Reconfiguration for Low Power Systems," TR 03-01, April 23, 2003.
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