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G. Madl and N. Dutt, "Real-time Analysis of Resource-Constrained Distributed Systems by Simulation-Guided Model Checking," ACM SIGBED Review: Special Issue on the RTSS Forum on Deeply Embedded Real-Time Computing, Volume 5, Number 1, January 2008.
Minyoung Kim, Hyunok Oh, Nikil Dutt, Alex Nicolau, Nalini Venkatasubramanian, "PBPAIR: An Energy-efficient Error-resilient Encoding Using Probability Based Power Aware Intra Refresh", ACM SIGMOBILE Mob. Comput. Commun. Rev. 10(3): 58-69, 2006.
A. Shrivastava, P. Biswas, A. Halambi, N. Dutt, and A. Nicolau, "Compilation Framework for Code Size Reduction using Reduced Bit-width ISAs," ACM Transactions on Design Automation of Electronic Systems ( TODAES), 2005.S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "A Scheduling Algorithm for Optimization and Planning in High level Synthesis," to appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, Pages 33-57, January 2005.
R. Kastner, Adam Kaplan, S. Ogrenci Memik, E. Bozorgzadeh, "Instruction Generation for Hybrid Reconfigurable Systems," ACM Transactions on Design Automation of Embedded Systems (TODAES), pp 605-627, Vol.7, No. 4, October 2002.
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S. Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of Bus-based Communication Architectures at the CCATB Abstraction," ACM Transactions on Embedded Computing Systems (TECS), Vol. 7, No. 2, February 2008.
Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian, "Energy-aware Cosynthesis of Real-time Multimedia Applications on MPSoCs Using Heterogeneous Scheduling Policies," ACM Transactions on Embedded Computing Systems (TECS). Vol. 7, No.2: Article 9, 2008.
C. Zhang, F. Vahid and W. Najjar, "A Highly Configurable Cache for Low Energy Embedded Systems," ACM Transactions on Embedded Computing Systems (TECS), Vol. 4, Issue 2, pp.
363-387,May 2005.
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P. Mishra and N. Dutt, "Automatic Modeling and Validation of Pipeline Specifications," ACM Transactions on Embedded Computing Systems (TECS), Vol 3, No. 1, pp 114-139, February 2004.
P. Mishra, M. Mamidipaka and N.D. Dutt, "Processor-Memory Co-Exploration using an Architecture Description Language," ACM Transactions on Embedded Computing Systems (TECS), Vol 3, No. 1, pp 140-162, February 2004.
P.D'Alberto and A. Nicolau, "R-Kleene: A High-Performance Divide-and-Conquer Algorithm for the All-Pair Shortest Path for Densely Connected Networks," Algorithmica, 2006.
download pdfC. Chen, E. Bozorgzadeh, A. Srivastava, and Majid Sarrafzadeh, "Budget Management with Applications," Algorithmica, Vol. 34, No. 3, pp 261-275, July 2002.
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P. Mishra and N. Dutt, "Architecture Description Languages for Programmable Embedded Systems," IEEE Computers & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends , Volume 152, Issue 03, June 2005.
S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, "Dynamically Increasing the Scope of Code Motions During the High-Level Synthesis of Digital Circuits," IEEE (British) Computers & Digital Techniques, Volume 150, Number 5, September 2003, pp 330-337.
O. Sinanoglu and A. Orailoglu, "Compacting Test Responses for Deeply Embedded SoC Cores," IEEE Design & Test of Computers, July-August 2003, pp 22-30.
S. Ozev, C. Olgaard, and A. Orailoglu, "Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers," IEEE Design and Test of Computers, September-October 2002, pp 82-91.
I. Bayraktaroglu and A. Orailoglu, "Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST,” IEEE Design and Test of Computers, January-February 2002, pp 42-53.
C.Park, J. Liu, and P. Chou, "B#: a Battery Emulator and Power Profiling Instrument,"
pp 150-159, March-April, 2005. S. Pasricha, M. Luthra, S. Mohapatra, N. Dutt, N. Venkatasubramanian, "Dynamic Backlight Adaptation for Low-Power Handheld Devices," pp 398-405, September-October 2004.
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S. Ozev, I. Bayraktaroglu, and A. Orailoglu, "Seamless Test of Digital Components in Mixed-Signal Paths," IEEE Design & Test of Computers, pp 44-55, January-February 2004.
I. G. Harris, "Fault Models and Test Generation for Hardware-Software Covalidation," IEEE Design and Test of Computers, Vol. 20, No. 4, July-August 2003.
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J. Suzuki and T. Suda, "A Middleware Platform for a Biologically-inspired Newtork Architecture Supporting Autonomous and Adaptive Applications," IEEE Journal on Selected Areas in Communications, Special issue on Intelligent Services and Applications in Next Generation Networks, Vol. 23, No. 2, February, 2005.
K. Fujii and T. Suda , "Semantics-based Dynamic Service Composition," IEEE Journal on Selected Areas in Communications, Special Issue on Autonomic Communication Systems,Vol. 23, No. 12, December 2005.
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P. Heydari , "Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise," To appear in IEEE Trans. on Circuits and Systems I , 2004.
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P. Heydari, S. Abbaspour, and M. Pedram, "Interconnect Energy Dissipation in High-Speed ULSI Circuits," to appear in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 2004.
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Jung-Yup Kang, Sandeep Gupta, and Jean-Luc Gaudiot, "An Efficient Data-Distribution Mechanism in a PIM (Processor-In-Memory) Architecture Applied to Motion Estimation," IEEE Transactions on Computers, Vol. 57, No. 3, March 2008.
P. Biswas , and N. Dutt, "Code Size Reduction in Heterogeneous-Connectivity-based DSPs using Instruction Set Extensions," IEEE Transactions on Computers , Vol 54, No. 10, October 2005, pp. 1216-1226.
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P.D'Alberto, A.Nicolau, A. Veidenbaum, and R.Gupta, "Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache,"
IEEE Transactions on Computers, February 2005.
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A. Gordon-Ross and F. Vahid, "Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware," IEEE Transactions on Computers, Special Issue-Embedded Systems, Microarchitecture, and Compilation Techniques , October 2005, Vol. 54, Issue 10, pp 1203-1215.
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S. Pasricha, N. Dutt, M. Ben-Romdhane, "BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464, August 2007.
E. Bozorgzadeh, S. Ghiasi, and M. Sarrafzadeh, "Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol. 23, No. 8, pp 1184- 1199 , August 2004.
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E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh, "Creating and Exploiting Flexibility in Rectilinear Steiner Trees," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 605-615, Vol. 22, No. 5, May 2003.
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Q. Zhang and I. G. Harris, "Partial BIST Insertion to Eliminate Data Correlation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003.
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T. Givargis and F. Vahid, "Platune: A Tuning Framework for System-on-Chip Platforms," IEEE Transactions on Computter-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 11, November 2002, pp 1317-1327.
I. G. Harris and R. Tessier, "Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 21, No. 11, November 2002.
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R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 777-790, vol. 21, No. 7, July 2002.
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I. Bayraktaroglu and A. Orailoglu, "Concurrent Test for Digital Linear Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001, pp 1132-1142.
T. Nakano and T. Suda, "Self-Organizing Network Services with Evolutionary Adaptation," IEEE Transactions on Neural Networks, Special Issue on Adaptive Learning Systems in Communication Networks, Vol. 16, No. 5 September 2005.
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P. Heydari and R. Mohanavelu, "Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches," to appear in IEEE Trans. on VLSI Systems, 2004.
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P. Heydari and M. Pedram, "Ground Bounce in Digital VLSI Circuits," IEEE Trans. on VLSI Systems, Vol. 11, No. 2, pp 180-193, April 2003.
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J. Zhu, D. D. Gajski, " An Ultra-Fast Instruction Set Simulator," IEEE Transactions on VLSI, Vol. 10, No. 3, June 2002, pp 363-373
S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, "FABSYN: Floorplan-aware Bus Architecture Synthesis," IEEE Trans. on VLSI, Vol 14, No. 3, March 2006, pp 241-253.
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T. Givargis, F. Vahid, and J. Henkel, "System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-Chip," IEEE/ACM Digest of Technical Papers for the International Conference on Computer Aided Design (ICCAD 2001), November 4-8, 2001, pp 25-30.
P. Mishra, N. Dutt, N. Krishnamurthy, M. Abadir, "A Methodology for Validation of Microprocessors using Symbolic Simulation," International Journal of Embedded Systems, Issue 1/2, 2005.
J. Lee, K. Choi, and N. Dutt, "Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures," International Journal of Embedded Systems, Issue 7, 2005 .
G. Madl, S. Abdelwahed, and D. Schmidt, "Verifying Distributed Real-time Properties of Embedded Systems via Graph Transformations and Model Checking," International Journal of Time-Critical Computing Systems, invited paper, 2005.
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E. Bozrgzadeh, S. Ogrenci Memik, X. Yang, and M. Sarrafzadeh, "Routability-driven Packing : Metrics and Algorithms for Cluster-based FPGAs," in Journal of Circuits, Systems, and Computers (JCSC), Vol. 13, No. 1, pp 77-100, February 2004.
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S. Arekapudi, F. Xin, J. Peng, I. G. Harris, "ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems," Journal for Circuits, Systems and Computers, Vol. 12, No. 3, June 2003.
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S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh, "Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System," to appear in Journal on Applied Signal Processing.
S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, N. Subramanian, "Co-optimization of Streaming Multimedia QoS and Backlight Power Consumption for Mobile Handheld Devices," Special Issue Journal of Korean Multimedia Society, pp 1-14, December 2003.
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Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian, Carolyn Talcott, "xTune: Online Verifiable Cross-Layer Adaptation for Distributed Real-Time Embedded Systems," IEEE International Real-Time Systems Symposium (RTSS'07) Ph.D. Forum, December 2007, Tucson, AZ, USA. Also published as SIGBED Review, Volume 5, Number 1, January 2008 Special Issue on the RTSS Forum on Deeply Embedded Real-Time Computing.
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