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S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, "On Computation and Resource Management in Networked Embedded Systems," International Conference on Parallel and Distributed Computing and Systems, pp 445-451,
Marina del Rey, CA, November 3-5, 2003.
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E. Gaudette, M. Moussa, and I. G. Harris, "A Method for the Evaluation of Behavioral Fault Models," IEEE High-Level Design, Validation, and Test Workshop (HLDVT), November 2003.download pdf
S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, and N. Venkatasubramanian, "Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices," ESTIMedia 2003, First Workshop on Embedded Systems for Real-Time Multimedia,
Newport Beach, CA, October 2003.
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S. Pasricha, and A. Veidenbaum, "Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches," International Conference on Computer Design (ICCD 2003),
San Jose, CA, October 2003
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L. Cai and D. Gajski, "A Transaction Level Modeling: An Overview," First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 19-24,
Newport Beach, CA, October 2003
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S. Cotterell, F. Vahid, W. Najjar and H. Hsieh, "First Results with eBlocks: Embedded Systems Building Blocks," First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 168-175
Newport Beach, CA, October 2003
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A. Koohi, N. Bagherzadeh, and C. Pan, "A Fast Parallel Reed-Solomon Decoder on a Reconfigurable Architecture," First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 59-64,
Newport Beach, CA, October 2003
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B. Mohebbi, E. Filho, R. Maestre, M. Davies, and F. Kurdahi, "A Case Study of Mapping a Software Defined Radio (SDR) Application on a Reconfigurable DSP Core," First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 103-108,
Newport Beach, CA, October 2003
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M. Reshadi, N. Bansa, P. Mishra and N. Dutt, "An Efficient Retargetable Framework for Instruction-Set Simulation," First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 13-18,
Newport Beach, CA, October 2003
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H. Yu, A. Gerstlauer, and D. Gajski, "RTOS Scheduling in Transaction Level Models," First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 31-36,
Newport Beach, CA,
October 2003
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D. A. Fernandes and I. G. Harris, "Application of Built in Self-Test for Interconnect Testing of FPGAs," IEEE International Test Conference, September 2003
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P. Chou, C. Park, J. Park, K. Pham, and J. Liu, "B#: a Battery Emulator and Power Profiling Instrument," 2003 International Symposium on Low Power Electronics and Design, pp 288-293,
Seoul, Korea, August 2003
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Heydari and Y. Zhang, "A Novel High Frequency, High-Efficiency, Differential Class-E Power Amplifier in 0.18um CMOS, Payam Heydari, and Ying Zhang," 2003 International Symposium on Low Power Electronics and Design, pp 455-458
Seoul, Korea, August 2003
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J. Lee, K. Choi, and N. Dutt, "Energy-Efficient Instruction Set Synthesis for Application-Specific Processors," 2003 International Symposium on Low Power Electronics and Design, pp 330-333,
Seoul, Korea, August 2003
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D. Nicolaescu, A. Veidenbaum, and A. Nicolau, "Reducing Data Cache Energy Consumption via Cached Load/Store Queue," 2003 International Symposium on Low Power Electronics and Design, pp 252-257,
Seoul, Korea, August 2003
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P. Mishra, A. Kejariwal, and N. Dutt, "Rapid Exploration of Pipelined Processors Through Automatic Generation of Synthesizable RTL Models," 14th IEEE Workshop on Rapid System Prototyping, pp 226-232,
San Diego, CA, June 2003
S. Abdi, D. Shin, and D. Gajski, "Automatic Communication Refinement for System Level Design," 40th Design Automation Conference, pp 300-305,
Anaheim, CA, June 2003
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E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Optimal Integer Delay Budgeting on Directed Acyclic Graphs," 40th Design Automation Conference, pp 300-305,
Anaheim, CA, June 2003
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T. Givargis, "Improving Indexing for Cache Miss Reduction in Embedded Systems," 40th Design Automation Conference, pp 875-880,
Anaheim, CA, June 2003
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D. Li, Q. Xie, and P. Chou, "Scalable Modeling and Optimization of Mode Transitions Based on Decoupled Power Management Architecture," 40th Design Automation Conference, pp 119-124,
Anaheim, CA, June 2003
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R. Lysecky and F. Vahid, "On-Chip Logic Minimization," 40th Design Automation Conference, pp 334-337,
Anaheim, CA, June 2003
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W. Rao, I. Bayraktaroglu, and A. Orailoglu, "Test Application Time and Volume Compression Through Overlapping," 40th Design Automation Conference, pp 732-737,
Anaheim, CA, June 2003
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M. Reshadi, P. Mishra and N. Dutt, "Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation," 40th Design Automation Conference, pp 758-763,
Anaheim, CA, June 2003
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G. Stitt, R. Lysecky, and F. Vahid, "Dynamic Hardware/Software Partitioning: A First Approach," 40th Design Automation Conference, pp 250-255,
Anaheim, CA, June 2003
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P. Mishra and N. Dutt, "A Methodology for Validation of Microprocessors using Equivalence Checking Communication Refinement for System Level Design," 4th Workshop on Microprocessor Test and Verification,
Austin, TX, May 2003
F. Doucet, R. Gupta, and S. Shukla, "Introspection in System-Level Language Frameworks: Meta-Level or Integrated," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 382-387,
Munich, Germany, March 2003
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A. Gerstlauer, H. Yu, and D. Gajski, "RTOS Modeling for System Level Design," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 130-135,
Munich, Germany, March 2003
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A. Ghosh and T. Givargis, "Analytical Design Space Exploration of Caches for Embedded Systems," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 650-655,
Munich, Germany, March 2003
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S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, "Dynamic Conditional Branch Balancing During the High-Level Synthesis of Control-Intensive Designs,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 270-275,
Munich, Germany, March 2003
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M. Mamidipaka and N. Dutt, "On-Chip Stack Based Memory Organization for Low Power Embedded Architectures," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1082-1087,
Munich, Germany, March 2003
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D. Nicolaescu, A. Veidenbaum, and A. Nicolau, "Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1064-1068,
Munich, Germany, March 2003
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C. Pan, N. Bagherzadeh, A. Kamalizad, and A. Koohi, "Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 468-473,
Munich, Germany, March 2003
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P. Petrov and A. Orailoglu, "Power Efficiency Through Application-Specific Instruction Memory Transformations," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 30-35,
Munich, Germany, March 2003
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W. Roa and A. Orailoglu, "Virtual Compression Through Test Vector Switching for Scan Based Design," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 104-109,
Munich, Germany, March 2003
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M. Sánchez-Élez, M. Férnandez, M. Anido, H. Du, N. Bagherzadeh, and R. Hermida, "Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures," Design, Automation, and Test in Europe Conference (DATE ‘03), pp 36-41,
Munich, Germany, March 2003
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Z. Zeng, Q. Zhang, I. G. Harris, and M. Ciesielski, "Fast Computation of Data Correlation Using BDDs," IEEE/ACM Design Automation and Test in Europe Conference (DATE '03), Munich, Germany, March 2003
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