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S. Cotterell and F. Vahid, "Synthesis of Customized Loop Caches for Core-Based Embedded Systems," IEEE/ACM International Conference on Computer-Aided Design, pp 655-662,
San Jose, CA, November 2002
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J. Lee, K. Choi, and N. Dutt, "Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPS," IEEE/ACM International Conference on Computer-Aided Design, pp 649-654,
San Jose, CA, November 2002
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O. Sinanoglu and A. Orailoglu, "A Novel Scan Architecture for Power-Efficient, Rapid Test," IEEE/ACM International Conference on Computer-Aided Design, pp 299-303,
San Jose, CA, November 2002
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G. Stitt and F. Vahid, "Hardware/Software Partitioning of Software Binaries," IEEE/ACM International Conference on Computer-Aided Design, pp 164-170,
San Jose, CA, November 2002
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S. Cotterell and F. Vahid, "Tuning of Loop Cache Architectures to Programs in Embedded System Designs," International Symposium on System Synthesis,
pp 8-13,
Kyoto, Japan, October 2002
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A. Gerstlauer and D. Gajski, "System-Level Abstraction Semantics," International Symposium on System Synthesis, pp 231-236,
Kyoto, Japan, October 2002
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S. Gupta, M. Reshadi, N. Saviou, N. Dutt, and A. Nicolau, "Dynamic Common Sub-Expression Elimination During Scheduling in High-Level Synthesis," International Symposium on System Synthesis, pp 261-266,
Kyoto, Japan, October 2002
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J. Liu, P. H. Chou, and N. Bagherzadeh, "Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors," International Symposium on System Synthesis, pp 14-19,
Kyoto, Japan, October 2002
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M. Mamidipaka, N. Dutt, and D. Hirschberg, "Efficient Power Reduction Techniques for Time Multiplexed Address Buses," International Symposium on System Synthesis, pp 207-212,
Kyoto, Japan, October 2002
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W. Mueller, R. Doemer, and A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis, pp 150-155,
Kyoto, Japan, October 2002
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J. Peng and D. Gajski, "Optimal Message Passing for Data Coherency in Distributed Architecture," International Symposium on System Synthesis,
pp 20-25,
Kyoto, Japan, October 2002
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P. Petrov and A. Orailoglu, "Low-Power Data Memory Communication for Application-Specific Embedded Processors," International Symposium on System Synthesis, pp 219-224,
Kyoto, Japan, October 2002
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N. Saviou, S. K. Shukla, and R. Gupta, "Efficient Simulation of Synthesis-Oriented System Level Designs," International Symposium on System Synthesis, pp 168-173,
Kyoto, Japan, October 2002
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S. Gupta, T. Kam, S. Rotem, N. Savoiu, N. Dutt, R. Gupta, and A. Nicolau, "Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks," 39th Design Automation Conference, pp 898-903,
New Orleans, LA, June 2002
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R. Lysecky, S. Cotterell, and F. Vahid, "A Fast On-Chip Profiler Memory," 39th Design Automation Conference, pp 28-33,
New Orleans, LA, June 2002
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B. Grattan, G. Stitt, and F. Vahid, "Codesign-Extended Applications," 10th International Symposium on Hardware/Software CoDesign, pp 1-6,
Estes Park, CO, May 2002
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J. Liu, P. Chou, and N. Bagherzadeh, "Communication Speed Selection for Embedded Systems with Networked Voltage-Scalable Processors," 10th International Symposium on Hardware/Software CoDesign, pp 169-174,
Estes Park, CO, May 2002
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M. Palesi and T. Givargis, "Multi-Objective Design Space Exploration Using Genetic Algorithms," 10th International Symposium on Hardware/Software CoDesign, pp 67-72,
Estes Park, CO, May 2002
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P. Petrov and A. Orailoglu, "Energy Frugal Tags in Reprogrammable I-Caches for Application-Specific Embedded Processors," 10th International Symposium on Hardware/Software CoDesign, pp 181-186,
Estes Park, CO, May 2002
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D. Li, P. Chou, and N. Bagherzadeh, "Mode Selection and Mode Dependency Modeling for Power-Aware Embedded Systems," 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 697-704,
Bangalore, India, January 2002
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P. Mishra, H. Tomiyama, A. Halambi, P. Grun, N. Dutt, and A. Nicolau, "Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language," 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002),
pp 458-463,
Bangalore, India, January 2002
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J. Peng, S. Abdi, and D. Gajski, "Automatic Model Refinement for Fast Architecture Exploration," 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 332-337,
Bangalore, India, January 2002
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A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, "Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints," Design, Automation and Test in Europe Conference, pp 168-175,
Paris, France, March 2002
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I. Bayraktaroglu and A. Orailodlu, "Gate Level Fault Diagnosis in Scan-Based BIST," Design, Automation and Test in Europe Conference, pp 376-381,
Paris, France, March 2002
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E. Cota, L. Carro, A. Orailoglu, and M. Lubaszewski, "Test Planning and Design Space Exploration in a Core-Based Environment," Design, Automation and Test in Europe Conference, pp 478-485,
Paris, France, March 2002
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F. Doucet, S. Shukla, R. Gupta, and M. Otsuka, "An Environment for Dynamic Component Composition for Efficient Co-Design," Design, Automation and Test in Europe Conference, pp 736-743,
Paris, France, March 2002
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P. Grun, N. Dutt, and A. Nicolau, "Memory System Connectivity Exploration," Design, Automation and Test in Europe Conference, pp 894-901,
Paris, France, March 2002
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A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, "An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Widths ISAs," Design, Automation and Test in Europe Conference, pp 402-408,
Paris, France, March 2002
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S. Irani, S. Shukla, and R. Gupta, "Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Saving States," Design, Automation and Test in Europe Conference, pp 117-123,
Paris, France, March 2002
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P. Mishra, H. Tomiyama, N. Dutt, and A. Nicolau, "Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units," Design, Automation and Test in Europe Conference, pp 36-43,
Paris, France, March 2002
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P. Petrov and A. Orailoglu, "Power Efficient Embedded Processor IP’s Through Application-Specific Tag Compression in Data Caches," Design, Automation and Test in Europe Conference, pp 1065-1071,
Paris, France, March 2002
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S. Reda and A. Orailoglu, "Reducing Test Application Time Through Test Data Mutation Encoding," Design, Automation and Test in Europe Conference,
pp 387-393,
Paris, France, March 2002
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M. Sánchez-Élez, M. Férnandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. Kurdahi, "A Complete Data Scheduler for Multi-Context Reconfigurable Architectures," Design, Automation and Test in Europe Conference, pp 547-552,
Paris, France, March 2002
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N. Savoiu, S. Shukla, and R. Gupta, "Automatic Concurrency Re-assignment in High Level System Models for Efficient System-Level Simulation," Design, Automation and Test in Europe Conference, pp 875-881,
Paris, France, March 2002
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W. Tang, R. Gupta, and A. Nicolau, "Power Savings in Embedded Processors Through Decode Filter Cache," Design, Automation and Test in Europe Conference, pp 443-448,
Paris, France, March 2002
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