Technical Reports

T. Givargis, “Optimal Cache Organization using an Allocation Tree,” TR 02-22, September 11, 2002. download pdf


D. Shin, D. D. Gajski, “Scheduling in RTL Design Methodology,” TR 02-11, April 12, 2002. download pdf


H. Yu and D. D. Gajski, “RTOS Modeling in System Level Synthesis," TR 02-25, August 30, 2002. download pdf


R. Jejurikar, R. Gupta, “Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems,” TR 02-21, June 21, 2002. download pdf


T. Givargis, “Optimal Indexing for Cache Miss Reduction in Embedded Systems,” TR 02-10, July 4, 2002. download pdf


R. Jejurikar, R. Gupta, “Computing Static Slowdown Factors under EDF Scheduling when Deadline less than Period,” TR 02-36, December 13, 2002. download pdf


L. Cai and D Gajski, "Specification Tuning of System-Level Design,” TR 02-20, June 6, 2002. download pdf


P. Zhang, D. D. Gajski, “RTL Design and Synthesis of Sequential Matrix Multiplication,” TR 02-09, April 3, 2002. download pdf


S. Gupta, N. Dutt, R. Gupta, A. Nicolau, “Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis,” TR 02-35, December 2002. download pdf


P. Mishra, M. Mamidipaka, N. Dutt, “A Framework for Memory Subsystem Exploration,” TR 02-19, May 24, 2002. download pdf


L. Cai, D. D. Gajski, “System Level Design Using SpecC Profiler,” TR 02-08, April 1, 2002. download pdf


J. Leei, K. Choi, N. Dutt, “Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing," TR 02-34, September 2002. download pdf


L. Cai, D. D. Gajski, “Parallelization Optimization of System-Level Specification,” TR 02-18, June 1, 2002. download pdf


L. Cai,D. D. Gajski, “Introduction of Design-Oriented Profiler of SpecC Language,” TR 02-07, March 1, 2002. download pdf


D. D. Gajski, “System-Level Design Flow: What is needed and what is not," TR 02-33, November 26, 2002. download pdf