Technical Reports

G Schirner and R. Doemer, "Using Result Oriented Modeling for Fast yet Accurate TLMs," TR 05-05, May 2005. download pdf


S. Choudhuri and T. Givargis, "Software Virtual Memory Management for MMU-Less Embedded Systems," TR 05-16, November 2005. download pdf


P. Chandriaiah, and R. Doemer, "Specification and Design of an MP3 Audio Decoder," TR 05-04, May 2005. download pdf


S. Abdi and D. Gajski, "A Tool for Functional Verfication of System Level Model Refinements," TR 05-15, October 2005. download pdf


G. Schirner and R. Doemer, "System Level Modeling of an AMBA Bus, " TR 05-03, April 2005. download pdf


S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Bus Matrix Communication Architecture Synthesis," TR 05-13, October 2005. download pdf


S. Banerjee and N. Dutt, "Very Fast Simulated Annealing for HW-SW Partitioning," TR 04-18, June 2004. download pdf


N. Savoiu, S. Shukla, and R. Gupta, "A Semantics-Preserving Reduction of Code-Annotated Well-formed Free Choice Petri Nets," TR 04-07, February 12, 2004. download pdf


S. Abdi and D. Gajski, "System Level Verification with Model Algebra," TR 04-29, November 9, 2004. download pdf


P. Chandraiah, H. Schirner, N. Srinivas, and R. Doemer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder," TR 04-17, June 21, 2004. download pdf


S. Pasricha, M. Ben-Romdhane, and N. Dutt, "High Level Design Space Exploration of Shared Bus Communication Architectures," TR 04-06, March 13, 2004. download pdf


M. Mamidipaka and N. Dutt, "eCACTI: An Enhanced Power Estimation Model for On-chip Caches," TR 04-28, September 14, 2004. download pdf


D. Shin, A. Gerstlauer, and D. Gajski, “Communication Link Synthesis for SoC,” TR 04-16, June 10, 2004. download pdf


P. Mishra and N. Dutt, "Functional Coverage Driven Test Generation for Validation of Pipelined Processors," TR 04-05, March 12, 2004. download pdf


S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, "Floorplan-aware Bus Architecture Synthesis," TR 04-27, October 2004. download pdf