Journal Articles

IEEE Transactions on Computers

Jung-Yup Kang, Sandeep Gupta, and Jean-Luc Gaudiot, “An Efficient Data-Distribution Mechanism in a PIM (Processor-In-Memory) Architecture Applied to Motion Estimation,” IEEE Transactions on Computers, Vol. 57, No. 3, March 2008.

P. Biswas , and N. Dutt, “Code Size Reduction in Heterogeneous-Connectivity-based DSPs using Instruction Set Extensions,” IEEE Transactions on Computers , Vol 54, No. 10, October 2005, pp. 1216-1226.
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P.D’Alberto, A.Nicolau, A. Veidenbaum, and R.Gupta, “Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache,” 
IEEE Transactions on Computers, February 2005.
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A. Gordon-Ross and F. Vahid, “Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware,” IEEE Transactions on Computers, Special Issue-Embedded Systems, Microarchitecture, and Compilation Techniques , October 2005, Vol. 54, Issue 10, pp 1203-1215.
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IEEE Transactions on Circuits and Systems

P. Heydari , “Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise,” To appear in IEEE Trans. on Circuits and Systems I , 2004.
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P. Heydari, S. Abbaspour, and M. Pedram, “Interconnect Energy Dissipation in High-Speed ULSI Circuits,” to appear in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 2004.
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IEEE Journal on Selected Areas in Communications

J. Suzuki and T. Suda, “A Middleware Platform for a Biologically-inspired Newtork Architecture Supporting Autonomous and Adaptive Applications,” IEEE Journal on Selected Areas in Communications, Special issue on Intelligent Services and Applications in Next Generation Networks, Vol. 23, No. 2, February, 2005.

K. Fujii and T. Suda , “Semantics-based Dynamic Service Composition,” IEEE Journal on Selected Areas in Communications, Special Issue on Autonomic Communication Systems,Vol. 23, No. 12, December 2005.
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IEEE Design & Test of Computers

Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, and Daniel Gajski, “Automatic TLM Generation for Early Validation of Multicore Systems,” pp 10-19, Vol. 28, No. 3, May-June 2011.
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Weiwei Chen, Xu Han, and Rainer Doemer, “Multicore Simulation of Transaction-Level Models using the SoC Environment,” pp 20-31, Vol. 28, No. 3, May-June 2011.
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C.Park, J. Liu, and P. Chou, “B#: a Battery Emulator and Power Profiling Instrument,”
pp 150-159, March-April, 2005.

S. Pasricha, M. Luthra, S. Mohapatra, N. Dutt, N. Venkatasubramanian, “Dynamic Backlight Adaptation for Low-Power Handheld Devices,” pp 398-405, September-October 2004.
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S. Ozev, I. Bayraktaroglu, and A. Orailoglu, “Seamless Test of Digital Components in Mixed-Signal Paths,” IEEE Design & Test of Computers, pp 44-55, January-February 2004.

I. G. Harris, “Fault Models and Test Generation for Hardware-Software Covalidation,” IEEE Design and Test of Computers, Vol. 20, No. 4, July-August 2003.
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IEEE Computers & Digital Techniques

P. Mishra and N. Dutt, “Architecture Description Languages for Programmable Embedded Systems,” IEEE Computers & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends , Volume 152, Issue 03, June 2005.

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, “Dynamically Increasing the Scope of Code Motions During the High-Level Synthesis of Digital Circuits,” IEEE (British) Computers & Digital Techniques, Volume 150, Number 5, September 2003, pp 330-337.

O. Sinanoglu and A. Orailoglu, “Compacting Test Responses for Deeply Embedded SoC Cores,”IEEE Design & Test of Computers, July-August 2003, pp 22-30.

S. Ozev, C. Olgaard, and A. Orailoglu, “Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers,” IEEE Design and Test of Computers, September-October 2002, pp 82-91.

I. Bayraktaroglu and A. Orailoglu, “Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST,” IEEE Design and Test of Computers, January-February 2002, pp 42-53.

 

ACM Transactions on Embedded Computing Systems (TECS)

Jelena Trajkovic, Alexander V. Veidenbaum, and Arun Kejariwal, “Improving SDRAM Access Energy Efficiency for Low-Power Embedded Systems,” ACM Transactions on Embedded Computer Systems, Vol. 7, No.3, April 2008.

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based Communication Architectures at the CCATB Abstraction,” ACM Transactions on Embedded Computing Systems (TECS), Vol. 7, No. 2, February 2008.

Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian, “Energy-aware Cosynthesis of Real-time Multimedia Applications on MPSoCs Using Heterogeneous Scheduling Policies,” ACM Transactions on Embedded Computing Systems (TECS). Vol. 7, No.2: Article 9, 2008.

C. Zhang, F. Vahid and W. Najjar, “A Highly Configurable Cache for Low Energy Embedded Systems,” ACM Transactions on Embedded Computing Systems (TECS), Vol. 4, Issue 2, pp.
363-387,May 2005.
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P. Mishra and N. Dutt, “Automatic Modeling and Validation of Pipeline Specifications,” ACM Transactions on Embedded Computing Systems (TECS), Vol 3, No. 1, pp 114-139, February 2004.

P. Mishra, M. Mamidipaka and N.D. Dutt, “Processor-Memory Co-Exploration using an Architecture Description Language,” ACM Transactions on Embedded Computing Systems (TECS), Vol 3, No. 1, pp 140-162, February 2004.

 

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A. Shrivastava, P. Biswas, A. Halambi, N. Dutt, and A. Nicolau, “Compilation Framework for Code Size Reduction using Reduced Bit-width ISAs,” ACM Transactions on Design Automation of Electronic Systems ( TODAES), 2005.

S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “A Scheduling Algorithm for Optimization and Planning in High level Synthesis,” to appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, Pages 33-57, January 2005.

R. Kastner, Adam Kaplan, S. Ogrenci Memik, E. Bozorgzadeh, “Instruction Generation for Hybrid Reconfigurable Systems,” ACM Transactions on Design Automation of Embedded Systems (TODAES), pp 605-627, Vol.7, No. 4, October 2002.
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Journal for Circuits, Systems and Computers (JCSC)

E. Bozrgzadeh, S. Ogrenci Memik, X. Yang, and M. Sarrafzadeh, “Routability-driven Packing : Metrics and Algorithms for Cluster-based FPGAs,” in Journal of Circuits, Systems, and Computers (JCSC), Vol. 13, No. 1, pp 77-100, February 2004.
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S. Arekapudi, F. Xin, J. Peng, I. G. Harris, “ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems,” Journal for Circuits, Systems and Computers, Vol. 12, No. 3, June 2003.
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Journal of Korean Multimedia Society (KSSM)

S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, N. Subramanian, “Co-optimization of Streaming Multimedia QoS and Backlight Power Consumption for Mobile Handheld Devices,” Special Issue Journal of Korean Multimedia Society, pp 1-14, December 2003.
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Algorithmica

C. Chen, E. Bozorgzadeh, A. Srivastava, and Majid Sarrafzadeh, “Budget Management with Applications,” Algorithmica, Vol. 34, No. 3, pp 261-275, July 2002.
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