Journal Articles

IEEE Computer

Martin Bichler, Kwei-Jay Lin: Service-Oriented Computing. IEEE Computer 39(3): 99-101 (2006)

 

Electronic Notes in Theoretical Computer Science (ENTCS)

Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta, Jean-Pierre Talpin: A Verification Approach for GALS Integration of Synchronous Components. Electr. Notes Theor. Comput. Sci. 146(2): 105-131 (2006)

 

Computer Architecture Letters (CAL)

Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron: Foreword. Computer Architecture Letters 5(2): (2006)

 

Communications for the ACM (CACM)

Mark D. Hill, Jean-Luc Gaudiot, Mary W. Hall, Joe Marks, Paolo Prinetto, Donna Baglio: A Wiki for discussing and promoting best practices in research. Commun. ACM 49(9): 63-64 (2006)

 

Parallel Computing

Won Woo Ro and Jean-Luc Gaudiot, “A Complexity-Effective Microprocessor Design with Decoupled Dispatch Queues,” to appear in Parallel Computing, in press (2008).

 

Journal on Applied Signal Processing (EURASIP)

S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh, “Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System,” to appear in Journal on Applied Signal Processing.

 

International Journal of Time-Critical Computing Systems

G. Madl, S. Abdelwahed, and D. Schmidt, “Verifying Distributed Real-time Properties of Embedded Systems via Graph Transformations and Model Checking,” International Journal of Time-Critical Computing Systems, invited paper, 2005.
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International Journal of Parallel Programming (IJPP)

Hsiao-Hsi Wang, Kuan-Ching Li, Ssu-Hsuan Lu, Chun-Chieh Yang, Jean-Luc Gaudiot , “Design and Implementation of an Agent Home Scheme Strategy for Prefetch-Based DSM Systems,”International Journal of Parallel Programming (IJPP), Springer.

 

International Journal of Embedded Systems

P. Mishra, N. Dutt, N. Krishnamurthy, M. Abadir, “A Methodology for Validation of Microprocessors using Symbolic Simulation,” International Journal of Embedded SystemsIssue 1/2, 2005.

J. Lee, K. Choi, and N. Dutt, “Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures,” International Journal of Embedded Systems, Issue 7, 2005.

 

Image and Vision Computing

Weisheng Duan, Falko Kuester, Jean-Luc Gaudiot, and Omar Hammami, “Automatic Object and Image Alignment using Fourier Descriptors,” to appear in Image and Vision Computing, in press (2008).

 

IEEE/ACM Digest of Technical Papers for the International Conference on Computer Aided Design

T. Givargis, F. Vahid, and J. Henkel, “System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-Chip,” IEEE/ACM Digest of Technical Papers for the International Conference on Computer Aided Design (ICCAD 2001), November 4-8, 2001, pp 25-30.

 

IEEE Transactions on VLSI

D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, “An Interactive Design Environment for C-based High-level Synthesis of RTL Processors,” IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 4, pp. 466-475, April 2008.

P. Heydari and R. Mohanavelu, “Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches,” to appear in IEEE Trans. on VLSI Systems2004.
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P. Heydari and M. Pedram, “Ground Bounce in Digital VLSI Circuits,” IEEE Trans. on VLSI Systems, Vol. 11, No. 2, pp 180-193, April 2003.
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J. Zhu, D. D. Gajski, ” An Ultra-Fast Instruction Set Simulator,” IEEE Transactions on VLSI, Vol. 10, No. 3, June 2002, pp 363-373

S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “FABSYN: Floorplan-aware Bus Architecture Synthesis,” IEEE Trans. on VLSI, Vol 14, No. 3, March 2006, pp 241-253.
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IEEE Transactions on Power Electronics

Farhan Simjee and Pai H. Chou, “Efficient Charging of Supercapacitors for Extended Lifetime of Wireless Sensor Nodes,” in IEEE Transactions on Power Electronics, Volume 23, Issue 3, May 2008. pages 1526–1536.

 

IEEE Transactions on Neural Networks

T. Nakano and T. Suda, “Self-Organizing Network Services with Evolutionary Adaptation,” IEEE Transactions on Neural Networks, Special Issue on Adaptive Learning Systems in Communication Networks, Vol. 16, No. 5 September 2005.
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

P. Chandraiah, R. Doemer: “Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1078-1090, June 2008.

S. Pasricha, N. Dutt, M. Ben-Romdhane, “BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464, August 2007.

E. Bozorgzadeh, S. Ghiasi, and M. Sarrafzadeh, “Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol. 23, No. 8, pp 1184- 1199 , August 2004.
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E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh, “Creating and Exploiting Flexibility in Rectilinear Steiner Trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 605-615, Vol. 22, No. 5, May 2003.
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Q. Zhang and I. G. Harris, “Partial BIST Insertion to Eliminate Data Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003.
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T. Givargis and F. Vahid, “Platune: A Tuning Framework for System-on-Chip Platforms,” IEEE Transactions on Computter-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 11, November 2002, pp 1317-1327.

I. G. Harris and R. Tessier, “Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 21, No. 11, November 2002.
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R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 777-790, vol. 21, No. 7, July 2002.
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I. Bayraktaroglu and A. Orailoglu, “Concurrent Test for Digital Linear Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001, pp 1132-1142.