Conference Proceedings

CODES + ISSS

L. Cai and D. Gajski, “A Transaction Level Modeling: An Overview,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 19-24,Newport Beach, CA, October 2003
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S. Cotterell, F. Vahid, W. Najjar and H. Hsieh, “First Results with eBlocks: Embedded Systems Building Blocks,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 168-175 Newport Beach, CA, October 2003 download pdf

A. Koohi, N. Bagherzadeh, and C. Pan, “A Fast Parallel Reed-Solomon Decoder on a Reconfigurable Architecture,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 59-64,Newport Beach, CA, October 2003 download pdf

B. Mohebbi, E. Filho, R. Maestre, M. Davies, and F. Kurdahi, “A Case Study of Mapping a Software Defined Radio (SDR) Application on a Reconfigurable DSP Core,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 103-108, Newport Beach, CA, October 2003 download pdf

M. Reshadi, N. Bansa, P. Mishra and N. Dutt, “An Efficient Retargetable Framework for Instruction-Set Simulation,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 13-18, Newport Beach, CA, October 2003 download pdf

H. Yu, A. Gerstlauer, and D. Gajski, “RTOS Scheduling in Transaction Level Models,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 31-36, Newport Beach, CA,October 2003 download pdf

 

International Conference on Computer Design (ICCD 2003

S. Pasricha, and A. Veidenbaum, “Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches,” International Conference on Computer Design (ICCD 2003), San Jose, CA, October 2003 download pdf

 

First Workshop on Embedded Systems for Real-Time Multimedia

S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, and N. Venkatasubramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices,” ESTIMedia 2003, First Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach, CA, October 2003. download pdf

 

IEEE High-Level Design, Validation, and Test Workshop

E. Gaudette, M. Moussa, and I. G. Harris, “A Method for the Evaluation of Behavioral Fault Models,” IEEE High-Level Design, Validation, and Test Workshop (HLDVT), November 2003. download pdf

 

15th IASTED International Conference on Parallel and Distributed Computing and Systems

S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, “On Computation and Resource Management in Networked Embedded Systems,” International Conference on Parallel and Distributed Computing and Systems, pp 445-451, Marina del Rey, CA, November 3-5, 2003.  download pdf

 

Design, Automation, and Test in Europe Conference (DATE ‘03)

F. Doucet, R. Gupta, and S. Shukla, “Introspection in System-Level Language Frameworks: Meta-Level or Integrated,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 382-387, Munich, Germany, March 2003 download pdf

A. Gerstlauer, H. Yu, and D. Gajski, “RTOS Modeling for System Level Design,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 130-135, Munich, Germany, March 2003 download pdf

A. Ghosh and T. Givargis, “Analytical Design Space Exploration of Caches for Embedded Systems,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 650-655, Munich, Germany, March 2003 download pdf

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, “Dynamic Conditional Branch Balancing During the High-Level Synthesis of Control-Intensive Designs,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 270-275, Munich, Germany, March 2003 download pdf

M. Mamidipaka and N. Dutt, “On-Chip Stack Based Memory Organization for Low Power Embedded Architectures,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1082-1087, Munich, Germany, March 2003 download pdf

D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1064-1068, Munich, Germany, March 2003 download pdf

C. Pan, N. Bagherzadeh, A. Kamalizad, and A. Koohi, “Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 468-473, Munich, Germany, March 2003 download pdf

P. Petrov and A. Orailoglu, “Power Efficiency Through Application-Specific Instruction Memory Transformations,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 30-35, Munich, Germany, March 2003 download pdf

W. Roa and A. Orailoglu, “Virtual Compression Through Test Vector Switching for Scan Based Design,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 104-109, Munich, Germany, March 2003 download pdf

M. Sánchez-Élez, M. Férnandez, M. Anido, H. Du, N. Bagherzadeh, and R. Hermida, “Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 36-41, Munich, Germany, March 2003
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Z. Zeng, Q. Zhang, I. G. Harris, and M. Ciesielski, “Fast Computation of Data Correlation Using BDDs,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’03), Munich, Germany, March 2003 download pdf

 

ASP-DAC/VLSI Design 2002

D. Li, P. Chou, and N. Bagherzadeh, “Mode Selection and Mode Dependency Modeling for Power-Aware Embedded Systems,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 697-704, Bangalore, India, January 2002 download pdf

P. Mishra, H. Tomiyama, A. Halambi, P. Grun, N. Dutt, and A. Nicolau, “Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 458-463, Bangalore, India, January 2002 download pdf

J. Peng, S. Abdi, and D. Gajski, “Automatic Model Refinement for Fast Architecture Exploration,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 332-337, Bangalore, India, January 2002 download pdf

 

10th International Symposium on Hardware/Software CoDesign

B. Grattan, G. Stitt, and F. Vahid, “Codesign-Extended Applications,” 10th International Symposium on Hardware/Software CoDesign, pp 1-6, Estes Park, CO, May 2002 download pdf

J. Liu, P. Chou, and N. Bagherzadeh, “Communication Speed Selection for Embedded Systems with Networked Voltage-Scalable Processors,” 10th International Symposium on Hardware/Software CoDesign, pp 169-174, Estes Park, CO, May 2002 download pdf

M. Palesi and T. Givargis, “Multi-Objective Design Space Exploration Using Genetic Algorithms,” 10th International Symposium on Hardware/Software CoDesign, pp 67-72, Estes Park, CO, May 2002 download pdf

P. Petrov and A. Orailoglu, “Energy Frugal Tags in Reprogrammable I-Caches for Application-Specific Embedded Processors,” 10th International Symposium on Hardware/Software CoDesign, pp 181-186, Estes Park, CO, May 2002 download pdf

 

39th Design Automation Conference

S. Gupta, T. Kam, S. Rotem, N. Savoiu, N. Dutt, R. Gupta, and A. Nicolau, “Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks,” 39th Design Automation Conference, pp 898-903, New Orleans, LA, June 2002 download pdf

R. Lysecky, S. Cotterell, and F. Vahid, “A Fast On-Chip Profiler Memory,” 39th Design Automation Conference, pp 28-33, New Orleans, LA, June 2002 download pdf

 

International Symposium on System Synthesis

S. Cotterell and F. Vahid, “Tuning of Loop Cache Architectures to Programs in Embedded System Designs,” International Symposium on System Synthesis, pp 8-13, Kyoto, Japan, October 2002 download pdf

A. Gerstlauer and D. Gajski, “System-Level Abstraction Semantics,” International Symposium on System Synthesis, pp 231-236, Kyoto, Japan, October 2002 download pdf

S. Gupta, M. Reshadi, N. Saviou, N. Dutt, and A. Nicolau, “Dynamic Common Sub-Expression Elimination During Scheduling in High-Level Synthesis,” International Symposium on System Synthesis, pp 261-266, Kyoto, Japan, October 2002 download pdf

J. Liu, P. H. Chou, and N. Bagherzadeh, “Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors,” International Symposium on System Synthesis, pp 14-19, Kyoto, Japan, October 2002 download pdf

M. Mamidipaka, N. Dutt, and D. Hirschberg, “Efficient Power Reduction Techniques for Time Multiplexed Address Buses,” International Symposium on System Synthesis, pp 207-212, Kyoto, Japan, October 2002 download pdf

W. Mueller, R. Doemer, and A. Gerstlauer, “The Formal Execution Semantics of SpecC,” International Symposium on System Synthesis, pp 150-155, Kyoto, Japan, October 2002 download pdf

J. Peng and D. Gajski, “Optimal Message Passing for Data Coherency in Distributed Architecture,” International Symposium on System Synthesis, pp 20-25, Kyoto, Japan, October 2002 download pdf

P. Petrov and A. Orailoglu, “Low-Power Data Memory Communication for Application-Specific Embedded Processors,” International Symposium on System Synthesis, pp 219-224, Kyoto, Japan, October 2002 download pdf

N. Saviou, S. K. Shukla, and R. Gupta, “Efficient Simulation of Synthesis-Oriented System Level Designs,” International Symposium on System Synthesis, pp 168-173, Kyoto, Japan, October 2002 download pdf

 

IEEE/ACM International Conference on Computer-Aided Design

S. Cotterell and F. Vahid, “Synthesis of Customized Loop Caches for Core-Based Embedded Systems,” IEEE/ACM International Conference on Computer-Aided Design, pp 655-662, San Jose, CA, November 2002 download pdf

J. Lee, K. Choi, and N. Dutt, “Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPS,” IEEE/ACM International Conference on Computer-Aided Design, pp 649-654, San Jose, CA, November 2002 download pdf

O. Sinanoglu and A. Orailoglu, “A Novel Scan Architecture for Power-Efficient, Rapid Test,” IEEE/ACM International Conference on Computer-Aided Design, pp 299-303, San Jose, CA, November 2002 download pdf

G. Stitt and F. Vahid, “Hardware/Software Partitioning of Software Binaries,” IEEE/ACM International Conference on Computer-Aided Design, pp 164-170, San Jose, CA, November 2002 download pdf

 

Design, Automation and Test in Europe Conference

A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, “Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints,” Design, Automation and Test in Europe Conference, pp 168-175, Paris, France, March 2002 download pdf

I. Bayraktaroglu and A. Orailodlu, “Gate Level Fault Diagnosis in Scan-Based BIST,” Design, Automation and Test in Europe Conference, pp 376-381, Paris, France, March 2002 download pdf

E. Cota, L. Carro, A. Orailoglu, and M. Lubaszewski, “Test Planning and Design Space Exploration in a Core-Based Environment,” Design, Automation and Test in Europe Conference, pp 478-485, Paris, France, March 2002 download pdf

F. Doucet, S. Shukla, R. Gupta, and M. Otsuka, “An Environment for Dynamic Component Composition for Efficient Co-Design,” Design, Automation and Test in Europe Conference, pp 736-743, Paris, France, March 2002 download pdf

P. Grun, N. Dutt, and A. Nicolau, “Memory System Connectivity Exploration,” Design, Automation and Test in Europe Conference, pp 894-901, Paris, France, March 2002
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A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, “An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Widths ISAs,” Design, Automation and Test in Europe Conference, pp 402-408, Paris, France, March 2002 download pdf

S. Irani, S. Shukla, and R. Gupta, “Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Saving States,” Design, Automation and Test in Europe Conference, pp 117-123, Paris, France, March 2002 download pdf

P. Mishra, H. Tomiyama, N. Dutt, and A. Nicolau, “Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units,” Design, Automation and Test in Europe Conference, pp 36-43, Paris, France, March 2002 download pdf

P. Petrov and A. Orailoglu, “Power Efficient Embedded Processor IP’s Through Application-Specific Tag Compression in Data Caches,” Design, Automation and Test in Europe Conference, pp 1065-1071, Paris, France, March 2002 download pdf

S. Reda and A. Orailoglu, “Reducing Test Application Time Through Test Data Mutation Encoding,” Design, Automation and Test in Europe Conference, pp 387-393, Paris, France, March 2002 download pdf

M. Sánchez-Élez, M. Férnandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. Kurdahi, “A Complete Data Scheduler for Multi-Context Reconfigurable Architectures,” Design, Automation and Test in Europe Conference, pp 547-552, Paris, France, March 2002 download pdf

N. Savoiu, S. Shukla, and R. Gupta, “Automatic Concurrency Re-assignment in High Level System Models for Efficient System-Level Simulation,” Design, Automation and Test in Europe Conference, pp 875-881, Paris, France, March 2002 download pdf

W. Tang, R. Gupta, and A. Nicolau, “Power Savings in Embedded Processors Through Decode Filter Cache,” Design, Automation and Test in Europe Conference, pp 443-448, Paris, France, March 2002 download pdf

 

DAC ’01

J. Liu, P. Chou, N. Bagherzadeh, and F. Kurdahi, “Power-Aware Scheduling Under Timing Constraints for Mission-Critical Embedded Systems,” Proceedings of the 38th Design Automation Conference, pp 840-845, Las Vegas, NV, June 2001

S. Gupta, N. Savoiu, S. Kim, N. Dutt, R. Gupta, and A. Nicolau, “Speculation Techniques for High Level Synthesis of Control Intensive Designs,” Proceedings of the 38th Design Automation Conference, pp 269-272, Las Vegas, NV, June 2001

I. Bayraktaroglu and A. Orailoglu, “Test Volume and Application Time Reduction Through Scan Chain Concealment,” Proceedings of the 38th Design Automation Conference, pp 151-155, Las Vegas, NV, June 2001

P. Petrov and A. Orailoglu, “Speeding Up Control-Dominated Applications Through Microarchitectural Customizations in Embedded Processors,” Proceedings of the 38th Design Automation Conference, pp 512-517, Las Vegas, NV, June 2001

 

IEEE Custom Integrated Circuits Conference

S. Almukhaizim, P. Petrov and A. Orailoglu, “Low-Cost, Software-Based Self-Test Methodologies for Performance Faults in Processor Control Subsystems,” Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2001

 

DATE 2001

P. Grun, N. Dutt, and A. Nicolau, “Access Pattern Based Local Memory Customization for Low Power Embedded Systems,” Proceedings of the Design Automation and Test in Europe Conference (DATE 2001), Munich, Germany, March 2001