Conference Proceedings

IEEE International Conference on Sensor and Ad Hoc Communications and Networks(SECON)

Location: Santa Clara, CA
Web Site: http://www.ieee-secon.org/2005/home.html

C.Park, K. Lahiri, and A. Raghunathan, “Battery Discharge Characteristics of Wireless Sensor Nodes: An Experimental Analysis ,” IEEE International Conference on Sensor and Ad Hoc Communications and Networks(SECON),September 26-29, 2005.

 

International Conference on Application-specific Systems, Architectures and Processors (IEEE ASAP 2005)

Location: Samos, Greece
Web Site: http://www.ece.uvic.ca/asap2005/

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Using TLM for Exploring Bus-based SoC Communication Architectures,” International Conference on Application-specific Systems, Architectures and Processors (IEEE ASAP 2005), July 2005.download pdf

 

IFIP International Conference on Embedded and Ubiquitous Computing (EUC’2005)

Location: Nagasaki, Japan
Web Site: http://euc05.euc-conference.org/

J. Lu, L. Bao and T. Suda, “Coverage aware Sensor Engagement in Dense Sensor Networks,” IFIP International Conference on Embedded and Ubiquitous Computing, December 6-9, 2005. download pdf

 

IPDPS’05 Workshop on NSF Next Generation Software Program

Location: Denver, CO

S. Mohapatra, R. Cornea, H. Oh, K. Lee, M. Kim, et al,“A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems,” IPDPS’05 Workshop on NSF Next Generation Software Program, April 2005.download pdf

 

IEEE International Conference on Intelligent Transportation Systems (ITSC 2005)

Location: Vienna, Austria
Web Site: http://www.itsc2005.at/

Y. Zhang, M. Lai, R. Klefstad, R. Lavanya, R. Jayakrishnan, ” A Distributed, Scalable, and Synchronized Framework for Large-Scale Microscopic Traffic Simulation,” IEEE International COnference on Intelligent Transportation Systems, September 13-16, 2005.

 

ACM INternational Conference on Supercomputing ( ICS 2005)

Location: Cambridge, MA
Website: http://ics05.csail.mit.edu/

R. Gonzales, A. Cristal, A. Veidenmbaum., and M. Valero, “An Asymmetric Clustered Processor based on Value Content,” ACM International Conference on Supercomputing (ICS 2005), June 2005.

 

IEEE International Symposium of Multimedia (ISM 2005)

Location: Irvine,CA
Website: http://ism2005.eecs.uci.edu/

C-Y. Shih, J.Hu, R. Klefstad, J. Lee, and D. Toulbert, “Marco- A Middleware Architecture for Distributed Multimedia Collaboration,” IEEE International Symposium of Multimedia (ISM 2005), December 12-14 2005.

 

IEEE/ACM International Conference on Information Processing in Sensor Networks (IPSN)

Location: Los Angeles, CA
Web Site: http://www.ece.wisc.edu/~ipsn05/

S. Cotterell, R. Mannion, F. Vahid, H. Hsieh, “eBlocks – An Enabling Technology for Basic Sensor Based Systems,” IPSN Track on Sensor Platform, Tools and Design Methods for Networked Embedded Systems (SPOTS), April 2005.download pdf

C. Park, J. Liu, and P. Chou , “Eco: an Ultra-Compact Low-Power Wireless Sensor Node for Real-Time Motion Monitoring ,” IEEE/ACM International Conference on Information Processing in Sensor Networks (IPSN), April 2005.download pdf

 

EMSOFT 2005

Location: Jersey City, NJ
Web Site: http://www.princeton.edu/~wolf/EMSOFT-2005/index.htm

G. Madl, S. Abdelwahed, “Model-based Analysis of Distributed Real-time Embedded System Composition,” EMSOFT, September 2005.download pdf

A. Kejariwal, A. Azevedo, A. Veidenbaum, and A. Nicolau, “High Performance Annotation-aware JVM for Java Cards,” EMSOFT, September 2005.

 

(ICDCS’05) Workshop on Services and Infrastructures for the Ubiquitous and Mobile Internet (SIUMI’05)

Location: Columbus, OH
Web Site: http://lia.deis.unibo.it/siumi05/

M.Kim, H. Oh, N.Dutt, A.Nicolau, and N.Venkatasubramanian, “Probability Based Power Aware Error Resilient Coding,”(ICDCS’05) Workshop on Services and Infrastructures for the Ubiquitous and Mobile Internet (SIUMI’05), June 2005.

 

International Conference on High Performance Computing (HiPC 2005)

Location: Goa, India
Web Site: http://www.hipc.org/hipc2005/

W.W Ro and J-L Gaudiot, “A Low-Complexity Issue Queue Design with Speculative

Pre-Execution,” International Conference on High Performance Computing(HiPC 2005), December 18-21, 2005.

 

IEEE Workshop on Embedded Systems for Real-Time Multimedia

Location: New York, NY
Web Site: http://peace.snu.ac.kr/ESTIMedia/

B. Gorjiara, D. Gajski, “Design Space Exploration of C Programs Using NISC: A Case-Study on DCT algorithm,” IEEE workshop on Embedded Systems for Real-Time Multimedia, April 2005. download pdf

A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, “Energy Analysis of Multimedia Watermarking in Mobile Handheld Devices,” IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), April 2005. download pdf

 

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2005 (CASES 2005)

Location: San Francisco, CA
Web Site: http://www.casesconference.org/cases2005/

H. Oh, N. Dutt, S. Ha, “Single Appearance Schedule with Dynamic Loop Count for the Minimum Data Buffer from Synchronous Dataflow Graphs,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

M. Ghodrat,T. Givargis, A. Nicolau, “Equivalence Checking of Arithmetic Expressions Using Fast Evaluation,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

A. Shrivastava, I. Issenin, N. Dutt, “Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

 

Design and Automation Conference (DAC 2005)

Location: Anaheim, CA
Web Site: http://www.dac.com/

S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, “Floorplan-aware Automated Synthesis of Bus-based Communication Architectures,” Design and Automation Conference (DAC 2005), June 2005. download pdf

S. Banerjee, E. Bozorgzadeh, N. Dutt, “Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration,” Design Automation Conference (DAC 2005), June 2005.

 

Design, Automation and Test in Europe Conference (DATE 05)

Location: Messe Munich, Germany
Website: www.date-conference.com

R. Lysecky, and F. Vahid, “A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores Using Dynamic Hardware/ Software Partitioning,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 18-23, March 7-11 2005 download pdf

A. Ghosh and T. Givargis, “LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 190-195, March 7-11 2005 download pdf

S. Abdi and D. Gajski, “Functional Validation of System Level Static Scheduling,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 542-547, March 7-11 2005 download pdf

P. Mishra and N. Dutt, “Functional Coverage Driven Test Generation for Validation of Pipelined Processors,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 678-683, March 7-11 2005 download pdf

A. Nacul and T. Givargas, “Lightweight Multitasking Support for Embedded Systems Using the Phantom Serialized Compiler,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany pp 742-747, March 7-11 2005 download pdf

S. Zhao and D. Gajski, “Defining an Enhanced RTL Semantics,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 548-553,, March 7-11 2005 download pdf

M. Reshadi and N. Dutt, “Generic Pipelined Processor Modeling and Cycle-Accurate Simulation Generation,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 786-791, March 7-11 2005 download pdf

I. Issenin and N. Dutt, “FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 808-813, March 7-11 2005 download pdf

R. Mannion, H. Hsieh, S. Cotterell and F. Vahid, “System Synthesis for Networks of Programmable Blocks,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 888-893, March 7-11 2005 download pdf

P.Biswas, S. Banerjee, N. Dutt, L. Pozzi and P. Ienne, “ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 1246-1251, March 7-11 2005 download pdf

A. Shrivastava, N. Dutt, A. Nicolau and E. Earlie, “PBEXPLORE: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors,”Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 1264-1270, March 7-11 2005 download pdf

G. Stitt and F. Vahid, “A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms Minimization,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 396-397 , March 7-11 2005 download pdf