Conference Proceedings

International Embedded Systems Symposium (IESS 2007) – June 2007

Location: Irvine, California, USA
Website: http://www.iess.org/

Ilya Issenin, Nikil Dutt, “Data Reuse Driven Memory and Network-on-Chip Co-Synthesis”

J. Trajkovic, D. Gajski, “Automatic Data Path Generation from C code for Custom Processors”

 

International Conference on Hardware/Software Codesign and System Synthesis

Location: Seoul, Korea
Website: http://www.ida.liu.se/conferences/codes/2006/

D. Shin, A. Gerstlauer, J. Peng, R. Dömer, D. Gajski, “Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration”, CODES+ISSS 2006, October 2006.
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G. Schirner, R. Dömer, “Accurate yet Fast Modeling of Real-Time Communication”, CODES+ISSS 2006, October 2006.
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Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian, “Design Space Exploration of Real-time Multi-media MPSoCs with Heterogeneous Scheduling Policies”, CODES+ISSS 2006, October 2006.

 

EuroMicro Conference on Digital System Design

Location: Dubrovnik, Croatia
Website: http://www.confman.org/dsd06/

I. Viskic, R. Dömer, “A Flexible, Syntax Independent Representation (SIR) for System Level Design Models”, DSD 2006, August 2006.download pdf

 

IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’06)

Location: San Jose, CA, USA
Website: http://www.rtas.org/rtas2006/index.htm

Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian, “Policy Construction and Validation for Energy Minimization in Cross Layered Systems: A Formal Method Approach”, RTAS’06 Work-in-Progress Session, April 2006.

 

Design, Automation, and Test in Europe (DATE 2006)

Location: Munich, Germany
Website: http://www.date-conference.com/

P. Biswas and N. Dutt, “Automatic Identification of Application-Specific Funtional Units with Architecturally Visible Storage,” DATE ’06, March 2006.download pdf

R. Cornea, A. Nicolau, N. Dutt, ” Software Annotations for Power Optimization on Mobile Devices,” DATE ’06, March 2006.download pdf

S. Pasricha and N. Dutt, “COSMECA: Application Specific Co-Syntesis of Memory and Communication Architectures fo MPSoC,” DATE ’06, March 2006.download pdf

G. Schirner and R. Doemer, “Quantitative Analysis of Transaction Level Models for the AMBA Bus,” DATE ’06, March 2006.download pdf

S. Park, A. Shrivastava, N. Dutt, E. Earlie, A. Nicolau, Y. Paek, ” Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processesors,” DATE ’06, March 2006.download pdf

 

Asia South Pacific Design Automation Conference 2006 (ASP-DAC 2006)

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

B. Gorjiara, M. Reshadi, D. Gajski, “Designing a Custom Architecture for DCT Using NISC Design Flow,” ASP-DAC’06 Design Contest, January 2006.download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC,” ASP-DAC’06, January 2006.download pdf

S. Banerjee, E Bozorgzadeh, N. Dutt, ” PARLGRAN: Parallelism Granularity Selection for Scheduling task chains on dynamically reconfigurable architectures,” ASP-DAC’06, January 2006.download pdf

H. Oh, N. Dutt, S. Ha, ” Memory Optimal Single Appearance Schedule wiht Dynamic Loop Count for Synchronous Dataflow Graphs,” ASP-DAC’06, January 2006.download pdf

H. Cho, S. Abdi, D. Gajski, “1D-19: Design and Implementation of a Duplex AMBA-TMS Transducer,” ASP-DAC’06, January 2006.download pdf

 

International Conference on Computer Aided Design

Location: San Jose, California
Website: http://www.iccad.com/geninfo.html

G. Schirner, R. Dömer, “Fast and Accurate Transaction Level Models using Result Oriented Modeling”, ICCAD ’06, November 2006.download pdf

 

International System-on-Chip Design Conference

Location: Seoul, Korea
Website: http://www.isocc.org/

R. Dömer, A. Gerstlauer, D. Shin, “Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components”, ISOCC ’06, October 2006.download pdf

 

Genetic and Evolutionary Computation Conference (GECCO 2005)

Location: Washington D.C.
Web Site: http://isgec.org/gecco-2005/

T. Suda, M. Moore, T. Nakano, R. Egashira, and A. Enomoto, “Exploratory Research on Molecular Communication between Nanomachines,” Genetic and Evolutionary Computation Conference, June 25-29 2005. download pdf

 

ACM/IFIP/USENIX International Middleware Conference-Middleware 2005

Location: Grenoble, France
Web Site: http://middleware05.objectweb.org/

K. Raman, Y. Zhang, M. Panahi, J.A. Colmenares, R. Klefstad, “RTZen: Highly Predictable, Real-time Java Middleware for Distributed and Embedded Systems,” Middleware 2005, November 28-December 2, 2005.

 

International Conference on Human Factors in Computing (CHI 2005)

Location: Portland, OR
Web Site: http://www.chi2005.org/

S. Cotterell and F. Vahid, “A Logic Block Enabling Logic Configuration by Non-Experts in Sensor Networks,” Conference on Human Factors in Computing (CHI), April 2005.download pdf

 

Semiconductor Research Corporation (SRC)-TECHCON 2005

Location: Portland, OR

A. Shrivastava, N. Dutt, A. Nicolau, E. Earlie, “Compiler-in-the-Loop; ADL-driven Early Architectural Exploration,” TECHCON 2005, October 2005.download pdf

 

IEEE Conference on Nanotechnology (NANO 2005)

Location: Nagoya, Japan
Web Site: http://www.mein.nagoya-u.ac.jp/IEEE-NANO/IEEE-NANO-2005/

T. Nakano, T. Suda, M. Moore, R. Egashira, A. Enomoto, and K. Arima, “Molecular Communication for Nanomachines Using Intercellular Calcium Signaling,” IEEE Conference on Nanotechnology, June 11-15, 2005.download pdf

 

International Conference on High Performance Computing in Asia Pacific Region (HPC Asia)

Location: Beijing, China
Web Site:http://www.ict.ac.cn/hpcasia2005/

P.D’Alberto and A. Nicolau, “Adaptive Strassen and ATLAS’s DGEMM: A Fast Square-Matrix Multiply for Modern High-Performance Systems,” International Conference on High Performance Computing in Asia Pacific Region (HPC Asia), November 30-December 3, 2005. download pdf

 

IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

Location: Napa, CA
Web Site: http://www.fccm.org/

S. Banerjee, E. Bozorgzadeh, and N. Dutt, “Considering runtime reconfiguration overhead in Task Graph Transformations for dynamically reconfigurable architectures,” IEEE symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005.