Conference Proceedings

Asia South Pacific Design Automation Conference 2006 (ASP-DAC 2006)

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

B. Gorjiara, M. Reshadi, D. Gajski, “Designing a Custom Architecture for DCT Using NISC Design Flow,” ASP-DAC’06 Design Contest, January 2006.download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC,” ASP-DAC’06, January 2006.download pdf

S. Banerjee, E Bozorgzadeh, N. Dutt, ” PARLGRAN: Parallelism Granularity Selection for Scheduling task chains on dynamically reconfigurable architectures,” ASP-DAC’06, January 2006.download pdf

H. Oh, N. Dutt, S. Ha, ” Memory Optimal Single Appearance Schedule wiht Dynamic Loop Count for Synchronous Dataflow Graphs,” ASP-DAC’06, January 2006.download pdf

H. Cho, S. Abdi, D. Gajski, “1D-19: Design and Implementation of a Duplex AMBA-TMS Transducer,” ASP-DAC’06, January 2006.download pdf

 

International Conference on Computer Aided Design

Location: San Jose, California
Website: http://www.iccad.com/geninfo.html

G. Schirner, R. Dömer, “Fast and Accurate Transaction Level Models using Result Oriented Modeling”, ICCAD ’06, November 2006.download pdf

 

International System-on-Chip Design Conference

Location: Seoul, Korea
Website: http://www.isocc.org/

R. Dömer, A. Gerstlauer, D. Shin, “Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components”, ISOCC ’06, October 2006.download pdf

 

International Conference on Hardware/Software Codesign and System Synthesis

Location: Seoul, Korea
Website: http://www.ida.liu.se/conferences/codes/2006/

D. Shin, A. Gerstlauer, J. Peng, R. Dömer, D. Gajski, “Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration”, CODES+ISSS 2006, October 2006.
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G. Schirner, R. Dömer, “Accurate yet Fast Modeling of Real-Time Communication”, CODES+ISSS 2006, October 2006.
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Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian, “Design Space Exploration of Real-time Multi-media MPSoCs with Heterogeneous Scheduling Policies”, CODES+ISSS 2006, October 2006.

 

EuroMicro Conference on Digital System Design

Location: Dubrovnik, Croatia
Website: http://www.confman.org/dsd06/

I. Viskic, R. Dömer, “A Flexible, Syntax Independent Representation (SIR) for System Level Design Models”, DSD 2006, August 2006.download pdf

 

IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’06)

Location: San Jose, CA, USA
Website: http://www.rtas.org/rtas2006/index.htm

Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian, “Policy Construction and Validation for Energy Minimization in Cross Layered Systems: A Formal Method Approach”, RTAS’06 Work-in-Progress Session, April 2006.

 

IEEE/ACM International Conference on Information Processing in Sensor Networks (IPSN)

Location: Los Angeles, CA
Web Site: http://www.ece.wisc.edu/~ipsn05/

S. Cotterell, R. Mannion, F. Vahid, H. Hsieh, “eBlocks – An Enabling Technology for Basic Sensor Based Systems,” IPSN Track on Sensor Platform, Tools and Design Methods for Networked Embedded Systems (SPOTS), April 2005.download pdf

C. Park, J. Liu, and P. Chou , “Eco: an Ultra-Compact Low-Power Wireless Sensor Node for Real-Time Motion Monitoring ,” IEEE/ACM International Conference on Information Processing in Sensor Networks (IPSN), April 2005.download pdf

 

EMSOFT 2005

Location: Jersey City, NJ
Web Site: http://www.princeton.edu/~wolf/EMSOFT-2005/index.htm

G. Madl, S. Abdelwahed, “Model-based Analysis of Distributed Real-time Embedded System Composition,” EMSOFT, September 2005.download pdf

A. Kejariwal, A. Azevedo, A. Veidenbaum, and A. Nicolau, “High Performance Annotation-aware JVM for Java Cards,” EMSOFT, September 2005.

 

(ICDCS’05) Workshop on Services and Infrastructures for the Ubiquitous and Mobile Internet (SIUMI’05)

Location: Columbus, OH
Web Site: http://lia.deis.unibo.it/siumi05/

M.Kim, H. Oh, N.Dutt, A.Nicolau, and N.Venkatasubramanian, “Probability Based Power Aware Error Resilient Coding,”(ICDCS’05) Workshop on Services and Infrastructures for the Ubiquitous and Mobile Internet (SIUMI’05), June 2005.

 

International Conference on High Performance Computing (HiPC 2005)

Location: Goa, India
Web Site: http://www.hipc.org/hipc2005/

W.W Ro and J-L Gaudiot, “A Low-Complexity Issue Queue Design with Speculative

Pre-Execution,” International Conference on High Performance Computing(HiPC 2005), December 18-21, 2005.

 

IEEE Workshop on Embedded Systems for Real-Time Multimedia

Location: New York, NY
Web Site: http://peace.snu.ac.kr/ESTIMedia/

B. Gorjiara, D. Gajski, “Design Space Exploration of C Programs Using NISC: A Case-Study on DCT algorithm,” IEEE workshop on Embedded Systems for Real-Time Multimedia, April 2005. download pdf

A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, “Energy Analysis of Multimedia Watermarking in Mobile Handheld Devices,” IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), April 2005. download pdf

 

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2005 (CASES 2005)

Location: San Francisco, CA
Web Site: http://www.casesconference.org/cases2005/

H. Oh, N. Dutt, S. Ha, “Single Appearance Schedule with Dynamic Loop Count for the Minimum Data Buffer from Synchronous Dataflow Graphs,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

M. Ghodrat,T. Givargis, A. Nicolau, “Equivalence Checking of Arithmetic Expressions Using Fast Evaluation,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

A. Shrivastava, I. Issenin, N. Dutt, “Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

 

Design and Automation Conference (DAC 2005)

Location: Anaheim, CA
Web Site: http://www.dac.com/

S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, “Floorplan-aware Automated Synthesis of Bus-based Communication Architectures,” Design and Automation Conference (DAC 2005), June 2005. download pdf

S. Banerjee, E. Bozorgzadeh, N. Dutt, “Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration,” Design Automation Conference (DAC 2005), June 2005.

 

Design, Automation and Test in Europe Conference (DATE 05)

Location: Messe Munich, Germany
Website: www.date-conference.com

R. Lysecky, and F. Vahid, “A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores Using Dynamic Hardware/ Software Partitioning,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 18-23, March 7-11 2005 download pdf

A. Ghosh and T. Givargis, “LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 190-195, March 7-11 2005 download pdf

S. Abdi and D. Gajski, “Functional Validation of System Level Static Scheduling,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 542-547, March 7-11 2005 download pdf

P. Mishra and N. Dutt, “Functional Coverage Driven Test Generation for Validation of Pipelined Processors,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 678-683, March 7-11 2005 download pdf

A. Nacul and T. Givargas, “Lightweight Multitasking Support for Embedded Systems Using the Phantom Serialized Compiler,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany pp 742-747, March 7-11 2005 download pdf

S. Zhao and D. Gajski, “Defining an Enhanced RTL Semantics,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 548-553,, March 7-11 2005 download pdf

M. Reshadi and N. Dutt, “Generic Pipelined Processor Modeling and Cycle-Accurate Simulation Generation,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 786-791, March 7-11 2005 download pdf

I. Issenin and N. Dutt, “FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 808-813, March 7-11 2005 download pdf

R. Mannion, H. Hsieh, S. Cotterell and F. Vahid, “System Synthesis for Networks of Programmable Blocks,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 888-893, March 7-11 2005 download pdf

P.Biswas, S. Banerjee, N. Dutt, L. Pozzi and P. Ienne, “ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 1246-1251, March 7-11 2005 download pdf

A. Shrivastava, N. Dutt, A. Nicolau and E. Earlie, “PBEXPLORE: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors,”Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 1264-1270, March 7-11 2005 download pdf

G. Stitt and F. Vahid, “A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms Minimization,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 396-397 , March 7-11 2005 download pdf

 

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2005)

Location: Jersey City, NY
Web Site: http://www.codes-isss.org/

M. Reshadi, D. Gajski, “A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf

A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Aggregating Processor Free Time for Energy Reduction,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf

D. Shin, A. Gerstlauer, R. Dömer, and D. Gajski, “Automatic Network Generation for System-on-Chip Communication Design,” International Conference on Hardware/Software Codesign and System Synthesis, September 2005.download pdf