Conference Proceedings

International Conference on Computer Design (ICCD 2007)

Location: Lake Tahoe, CA
Website: http://www.iccd-conference.org/2007/

A.H. Gholamipour, E. Bozorgzadeh, S. Banerjee, “Energy-Aware Coprocessor Selection for Embedded Processors on FPGAs,” IEEE International Conference on Computer Design (ICCD), October 2007.

Houman Homayoun and Alexander V. Veidenbaum, “Reducing Power Consumption in Peripheral Circuits of L2 caches,” Proc. IEEE Intl. Conference on Computer Design, Lake Tahoe, Oct. 2007

B. Gorjiara, D. Gajski, “A Novel Profile-Driven Technique for Simultaneous Power and Code-size Optimization of Nanocoded IPs,” International Conference on Computer Design (ICCD), October 2007.

Y. Park, S. Pasricha, F.J. Kurdahi, N. Dutt, “System Level Power Estimation Methodology with H.264 Decoder Prediction IP Case Study,” International Conference on Computer Design (ICCD 2007), Lake Tahoe, October 2007.

 

International Embedded Systems Symposium (IESS 2007) – June 2007

Location: Irvine, California, USA
Website: http://www.iess.org/

Ilya Issenin, Nikil Dutt, “Data Reuse Driven Memory and Network-on-Chip Co-Synthesis”

J. Trajkovic, D. Gajski, “Automatic Data Path Generation from C code for Custom Processors”

 

IEEE Conference on Automation Science and Engineering (CASES 2007)

Website: http://www.casesconference.org/

D.Cho, I. Issenin, N.D. Dutt, and Y. Paek, “Software Controlled Memory Layout Reorganization for Irregular Array Access Patterns,” Proc. Of the 2007 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2007), Salzburg, Austria, October 2007.

Alex Nicolau, Carmen Badea, Alexander V. Veidenbaum, “A Simplified Java Bytecode Compilation System for Resource-Constrained Embedded Processors”,  Proc. IEEE CASES ’07, Salzburg, Austria September 30–October 3, 2007.

 

International Conference on Formal Methods for Open Object-Based Distributed Systems (FMOODS’07)

Location: Paphos, Cyprus.
Website: http://www.liacs.nl/~marcello/FMOODS/index.htm

Minyoung Kim, Mark-Oliver Stehr, Carolyn Talcott, Nikil Dutt, Nalini Venkatasubramanian, “A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems”, LNCS 4468 pages 285-300

 

IEEE Custom Integrated Circuits Conference (CICC)

Location: San Jose, CA
Website: http://www.ieee-cicc.org/

Aminghasem Safarian, Lei Zhou, and Payam Heydari, “A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.

Vipul Jain, Sriramkumar Sundararaman, and Payam Heydari,  “A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.

Deyi Pi, Byung-Kwan Chun, and Payam Heydari,  “A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007 [nominated for Best Paper Award].

 

Asia South Pacific Design Automation Conference 2007 (ASP-DAC 2007)

Location: Yokohama, Japan
Website: http://www.aspdac.com/

G. Schirner, A. Gerstlauer, R. Dömer, “Abstract, Multifaceted Modeling of Embedded Processors for System-Level Design“, ASP-DAC’07 , January 2007.download pdf

P. Chandraiah, J. Peng, R. Dömer, “Creating Explicit Communication in SoC Models Using Interactive Re-Coding”,S. Pasricha, N. Dutt, M. Ben-Romdhane, ASP-DAC’07, January 2007.download pdf

 

Symposium on Parallel Computing with FPGA’s (ParaFPGA)

Location: Juelich, Germany

Alex Nicolau, Furlong, J., A. Felch, J. Nageswaran, N. Dutt, A. Veidenbaum, A. Chandrashekar, and R. Granger,  “A Brain Derived Vision System Accelerated by FPGAs,” Proc. ParaFPGA: Parallel Computing with FPGA’s, September 4-7, 2007.

J. Furlong, A. Felch, J. Moorkanikara, N. Dutt, A. Nicolau, A. Veidenbaum, A. Chandrashekar, R. Granger, “Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements,” Proceedings of the 2007 Symposium on Parallel Computing with FPGA’s (ParaFPGA), Juelich, Germany, September 2007.

 

International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS)

Date: Sept. 30 – Oct. 5, 2007
Location: Salzburg, Austria
Website: http://www.ida.liu.se/cnferences/codes

G. Stitt and F. Vahid, “Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98

P. Chandraiah, R. Dömer: “Pointer Re-coding for Creating Definitive MPSoC Models”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2007: pp. 33-38

 

ACM SIGPLAN Principles and Practice of Parallel Computing (PPOPP 2007)

Location: San Jose, CA
Website: http://ftg.lbl.gov/ppopp07/

Alex Nicolau, Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, “Tight analysis of the performance potential of thread speculation using spec CPU 2006”, Proc.  PPOPP 2007: 215-225, June 2007.

 

IEEE International High-Level Design

Yu, L. & Abdi, S., “Automatic TLM Generation for C-Based MPSoC Design,” Proceedings of the 2007 IEEE International High-Level Design, Validation and Test Workshop, November 2007.

 

21st ACM International Conference on Supercomputing (ICS 2007)

Location: Seattle, WA
Website: http://ics07.ac.upc.edu/

Alex Nicolau,  P.D’Alberto, “Adaptive Strassen’s Matrix Multiplication”, Proc. ACM  21st International Conference on Supercomputing, June 2007.

 

IEEE Asian Solid-State Circuits Conference (A-SSCS)

Deyi Pi, Byung-Kwan Chun, and Payam Heydari, “A 2.5-3.2GHz Continuously-Tuned Varactor-Less LC-VCO,” IEEE Asian Solid-State Circuits Conference (A-SSCS), Nov. 2007.

 

IEEE International Parallel & Distributed Processing Symposium (IPDPS 2007), March 26-30, 2007

Location: Long Beach, California
Website: http://www.ipdps.org/

Kyueun Yi and Jean-Luc Gaudiot, “Architectural Support for Network Applications on Simultaneous MultiThreading Processors”
Akira Hatanaka , Nader Bagherzadeh, “A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template”

 

6th International Symposium on High Performance Computing (ISHPC-VI)

Alex Nicolau, D. Nicolaescu & A. Veidenbaum, “Using a Way Cache to Improve Performance of Set-Associate Caches,” 6th International Symposium on High Performance Computing (ISHPC-VI), Lecture Notes on Computer Science, Springer Verlag Pub. (to appear) October  2007.

 

International Conference on Computer Aided Design

Location: San Jose, California
Website: http://www.iccad.com/geninfo.html

G. Schirner, R. Dömer, “Fast and Accurate Transaction Level Models using Result Oriented Modeling”, ICCAD ’06, November 2006.download pdf