Location: Las Vegas, Nevada, USA
Website: http://www.itng.info/
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh, “Design and Analysis of a Feasible Network-on-Chip(NoC) Architecture”
Location: Salzburg, Austria
Website: http://www.emsoft.org/
G. Madl, S. Abdelwahed, and N. Dutt, “Performance Estimation of Distributed Real-time Embedded Systems by Discrete Event Simulations,” Proceedings of the 7th Annual ACM Conference on Embedded Software(EMSOFT’07) , October 2007.
Location: San Diego, USA.
Website: http://www.dac.com
Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan, “Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation”
Location: Salzburg, Austria
M. Kim, M. Stehr, C. Talcott, N. Dutt and N. Venkatasubramanian, “Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters,” Proceedings of the 5th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS’07), Salzburg, Austria, October 2007.
Location: Monterey, California
Website: http://conferences.ece.ubc.ca/isfpga2007/main_intro.html
B. Gorjiara, D. Gajski, “FPGA-friendly Code Compression Technique for Statically Scheduled Horizontal Microcoded Custom IPs”
Location: Lake Tahoe, CA
Website: http://www.iccd-conference.org/2007/
A.H. Gholamipour, E. Bozorgzadeh, S. Banerjee, “Energy-Aware Coprocessor Selection for Embedded Processors on FPGAs,” IEEE International Conference on Computer Design (ICCD), October 2007.
Houman Homayoun and Alexander V. Veidenbaum, “Reducing Power Consumption in Peripheral Circuits of L2 caches,” Proc. IEEE Intl. Conference on Computer Design, Lake Tahoe, Oct. 2007
B. Gorjiara, D. Gajski, “A Novel Profile-Driven Technique for Simultaneous Power and Code-size Optimization of Nanocoded IPs,” International Conference on Computer Design (ICCD), October 2007.
Y. Park, S. Pasricha, F.J. Kurdahi, N. Dutt, “System Level Power Estimation Methodology with H.264 Decoder Prediction IP Case Study,” International Conference on Computer Design (ICCD 2007), Lake Tahoe, October 2007.
Location: Irvine, California, USA
Website: http://www.iess.org/
Ilya Issenin, Nikil Dutt, “Data Reuse Driven Memory and Network-on-Chip Co-Synthesis”
J. Trajkovic, D. Gajski, “Automatic Data Path Generation from C code for Custom Processors”
Website: http://www.casesconference.org/
D.Cho, I. Issenin, N.D. Dutt, and Y. Paek, “Software Controlled Memory Layout Reorganization for Irregular Array Access Patterns,” Proc. Of the 2007 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2007), Salzburg, Austria, October 2007.
Alex Nicolau, Carmen Badea, Alexander V. Veidenbaum, “A Simplified Java Bytecode Compilation System for Resource-Constrained Embedded Processors”, Proc. IEEE CASES ’07, Salzburg, Austria September 30–October 3, 2007.
Location: Paphos, Cyprus.
Website: http://www.liacs.nl/~marcello/FMOODS/index.htm
Minyoung Kim, Mark-Oliver Stehr, Carolyn Talcott, Nikil Dutt, Nalini Venkatasubramanian, “A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems”, LNCS 4468 pages 285-300
Location: San Jose, CA
Website: http://www.ieee-cicc.org/
Aminghasem Safarian, Lei Zhou, and Payam Heydari, “A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.
Vipul Jain, Sriramkumar Sundararaman, and Payam Heydari, “A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.
Deyi Pi, Byung-Kwan Chun, and Payam Heydari, “A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007 [nominated for Best Paper Award].
Location: Yokohama, Japan
Website: http://www.aspdac.com/
G. Schirner, A. Gerstlauer, R. Dömer, “Abstract, Multifaceted Modeling of Embedded Processors for System-Level Design“, ASP-DAC’07 , January 2007.download pdf
P. Chandraiah, J. Peng, R. Dömer, “Creating Explicit Communication in SoC Models Using Interactive Re-Coding”,S. Pasricha, N. Dutt, M. Ben-Romdhane, ASP-DAC’07, January 2007.download pdf
Location: Juelich, Germany
Alex Nicolau, Furlong, J., A. Felch, J. Nageswaran, N. Dutt, A. Veidenbaum, A. Chandrashekar, and R. Granger, “A Brain Derived Vision System Accelerated by FPGAs,” Proc. ParaFPGA: Parallel Computing with FPGA’s, September 4-7, 2007.
J. Furlong, A. Felch, J. Moorkanikara, N. Dutt, A. Nicolau, A. Veidenbaum, A. Chandrashekar, R. Granger, “Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements,” Proceedings of the 2007 Symposium on Parallel Computing with FPGA’s (ParaFPGA), Juelich, Germany, September 2007.
Date: Sept. 30 – Oct. 5, 2007
Location: Salzburg, Austria
Website: http://www.ida.liu.se/cnferences/codes
G. Stitt and F. Vahid, “Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98
P. Chandraiah, R. Dömer: “Pointer Re-coding for Creating Definitive MPSoC Models”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2007: pp. 33-38
Location: San Jose, CA
Website: http://ftg.lbl.gov/ppopp07/
Alex Nicolau, Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, “Tight analysis of the performance potential of thread speculation using spec CPU 2006”, Proc. PPOPP 2007: 215-225, June 2007.
Location: Yokohama, Japan
Web Site: http://www.aspdac.com/
B. Gorjiara, M. Reshadi, D. Gajski, “Designing a Custom Architecture for DCT Using NISC Design Flow,” ASP-DAC’06 Design Contest, January 2006.download pdf
S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC,” ASP-DAC’06, January 2006.download pdf
S. Banerjee, E Bozorgzadeh, N. Dutt, ” PARLGRAN: Parallelism Granularity Selection for Scheduling task chains on dynamically reconfigurable architectures,” ASP-DAC’06, January 2006.download pdf
H. Oh, N. Dutt, S. Ha, ” Memory Optimal Single Appearance Schedule wiht Dynamic Loop Count for Synchronous Dataflow Graphs,” ASP-DAC’06, January 2006.download pdf
H. Cho, S. Abdi, D. Gajski, “1D-19: Design and Implementation of a Duplex AMBA-TMS Transducer,” ASP-DAC’06, January 2006.download pdf