Conference Proceedings

35th International Symposium on Computer Architecture (ISCA 2008) – June 21-25, 2008

Location: Beijing, China
Website: http://isca2008.cs.princeton.edu/

Miquel Pericas, Adrian Cristal, Francisco J. Cazorla, Ruden Gonzalez, Alex Veidenbaum, Daniel A. Jimenez, and Mateo Valero, “A Two-Level Load/Store Queue based on Execution Locality,” Proc. 35th International Symposium on Computer Architecture (ISCA) June 2008.

 

ACM SIGPLAN Symposium on Principles and practice of parallel programming (PPOPP’08)

Location: Salt Lake City, Utah
Website: http://research.ihost.com/ppopp08/

Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, “Cache-Aware Iteration Space Partitioning,” Proc. of the ACM SIGPLAN Symposium on Principles and practice of parallel programming (PPOPP) 2008.

 

IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2008) – June 15-17, 2008

Location: Atlanta, GA
Website: http://www.rfic2008.org/

Fred Tzeng, Amin Jahanian, Deyi Pi, Payam Heydari, “A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End for Spatial Multiplexing, Spatial Diversity and Beamforming,” IEEE RFIC Symposium, June 2008. (Nominated for the Best Paper Award).

 

Asia South Pacific Design Automation Conference 2008 (ASP-DAC 2008) – January 21-24, 2008

Location: Seoul, Korea
Website: http://www.aspdac.com/

S. Pasricha, N. Dutt, “ORB: An On-chip Optical Ring Bus Communication Architecture for Multi-Processor Systems-on-Chip,” IEEE Asia & South Pacific Design Automation Conference (ASPDAC 2008), Seoul, Korea, January 2008.

Gunar Schirner, Andreas Gerstlauer, Rainer Doemer, “Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications,” Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, January 2008.

Love Singhal, Sejong Oh and Eli Bozorgzadeh, “Statistical Power Profile Correlation for Realistic Thermal Estimation,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, January 2008.

A. Shrivastava, I. Issenin , N. Dutt, “A Compiler-in-the-Loop Framework to Explore Horizontally Partitioned Cache Architectures,” Proceedings of ASPDAC-2008, January 2008.

N. Dutt, “Quo Vadis, BTSoCs (Billion Transistor SoCs)?” Panel Position Statement, Proceedings of ASPDAC-2008, January 2008.

 

ACM SIGPLAN/SIGBED 2008 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2008) – June 12-13, 2008

Location: Tucson, AZ
Website: http://www.sigplan.org/lctes.htm

Carmen Badea, Alexandru Nicolau, and Alexander V. Veidenbaum, “Impact of JVM superoperators on energy consumption in resource-constrained embedded systems,” Proc. of the ACM SIGPLAN-SIGBED conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2008.

D. Cho, I. Issenin, S. Pasricha, N. Dutt, and Y. Paek,  “Compiler Driven Data Layout Optimization for Regular/Irregular Array Access Patterns,”  Proceedings of ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES08) , June 2008.

Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum, “Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors,” ACM SIGPLAN/SIGBED 2008 Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2008.

 

IEEE VLSI Design (VLSID 2008) – January 4-8, 2008

Location: HICC, Hyderabad, India
Website: http://www.vlsiconference.com/vlsi2008/

S. Pasricha, Y. Park, S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures,” IEEE VLSI Design Conference (VLSID 2008), Bangalore, India, January 2008.

D. Kannan, A. Gupta, A. Shrivastava, N. Dutt, and F. Kurdahi, “PTSMT: A Tool for Cross-Level Power, Performance and Temperature Exploration of SMT Processors,” Proceedings of the 2008 International Conference on VLSI Design, Hyderabad, India, January, 2008.

 

IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08) – June 12-13, 2008

Location: Anaheim, CA
Website: http://www.nanoarch.org/08/index.html

S. Pasricha, N. Dutt, and F. Kurdahi. “System Level Performance Analysis of Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors,” Proceedings of  the IEEE/ACM International Symposium on NanoScale Architectures (NanoArch 2008), Anaheim, CA, June 2008.

 

Design Automation Conference (DAC 2008) – June 8-13, 2008

Location: Anaheim, CA, United States
Website: http://www.dac.com/

N. Dutt, “ESL Hand-off: Fact or EDA Fiction?” Panel Position Statement, Proceedings of the Design Automation Conference 2008 (DAC 2008), Anaheim, CA, June 2008.

Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, and Alexander V. Veidenbaum, “Dynamic Register File Resizing and Frequency Scaling to Improve Embedded Processor Performance and Energy-Delay Efficiency,” Proc. of the Design Automation Conference (DAC) 2008.

 

IEEE Symposium on Application Specific Processors (SASP 2008) – June 8-9, 2008

Location: Anaheim, CA
Website: http://www.sasp-conference.org/

J. Trajkovic, D. Gajski, “Custom Processor Core Construction from C Code,” In Proceedings of Sixth IEEE Symposium on Application Specific Processors (June 2008).

 

IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’08) – April 22-24, 2008

Location: St. Louis, MO
Website: http://www.rtas.org/rtas2008/

Minyoung Kim, Daniel Massaguer, Nikil Dutt, Sharad Mehrotra, Shangping Ren, Mark-Oliver Stehr, Carolyn Talcott, Nalini Venkatasubramanian, “A Semantic Framework for Reconfiguration of Instrumented Cyber Physical Spaces,” Second Workshop on Event-based Semantics (WEBS’08) in conjunction with IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’08) in part of CPSWEEK, Apr. 2008, St. Louis, MO, USA.

 

International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS)

Date: Sept. 30 – Oct. 5, 2007
Location: Salzburg, Austria
Website: http://www.ida.liu.se/cnferences/codes

G. Stitt and F. Vahid, “Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98

P. Chandraiah, R. Dömer: “Pointer Re-coding for Creating Definitive MPSoC Models”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2007: pp. 33-38

 

ACM SIGPLAN Principles and Practice of Parallel Computing (PPOPP 2007)

Location: San Jose, CA
Website: http://ftg.lbl.gov/ppopp07/

Alex Nicolau, Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, “Tight analysis of the performance potential of thread speculation using spec CPU 2006”, Proc.  PPOPP 2007: 215-225, June 2007.

 

IEEE International High-Level Design

Yu, L. & Abdi, S., “Automatic TLM Generation for C-Based MPSoC Design,” Proceedings of the 2007 IEEE International High-Level Design, Validation and Test Workshop, November 2007.

 

21st ACM International Conference on Supercomputing (ICS 2007)

Location: Seattle, WA
Website: http://ics07.ac.upc.edu/

Alex Nicolau,  P.D’Alberto, “Adaptive Strassen’s Matrix Multiplication”, Proc. ACM  21st International Conference on Supercomputing, June 2007.

 

IEEE Asian Solid-State Circuits Conference (A-SSCS)

Deyi Pi, Byung-Kwan Chun, and Payam Heydari, “A 2.5-3.2GHz Continuously-Tuned Varactor-Less LC-VCO,” IEEE Asian Solid-State Circuits Conference (A-SSCS), Nov. 2007.