P. K. Jha, C. Ramachandran, F. Kurdahi, N. Dutt: Towards Better Accounting of Physical Design Effects in High Level Synthesis in “Novel Approaches in Logic and Architecture Synthesis”, A. Mignotte and G. Saucier, Editors, Chapman and Hall 1995.
D. Gajski, J. Zhu, R. Dömer: “Essential Issues in Codesign”, Chapter 1 in “Hardware/Software Co-Design: Principles and Practice” (ed. J. Staunstrup, W. Wolf), Kluwer Academic Publishers, Boston, October 1997. (ISBN 0-7923-8013-4)
D. Gajski, R. Dömer, J. Zhu: “IP-Centric Method ology and Design with the SpecC Language” , Chapter 10 in “System-Level Synthesis” (ed. A. Jerraya, J. Mermet), Kluwer Academic P ublishers, Dordrecht, May 1999. (ISBN 0-7923-5748-5)
Babak Daneshrad and Ahmed M. Eltawil “ Integrated Circuit Technologies for Wireless Communications ,” Wireless Multimedia Network Technologies, Kluwer Academic Publishers, Chapter 13, Sept. 1999.
D. Gajski, R. Dömer, J. Zhu: “IP-centric Methodology and Specification Language”, Chapter in “Distributed and Parallel Embedded Systems” (ed. F. Rammig), Kluwer Academic Publishers, Boston, September 1999. (ISBN 0-7923-8614-0)
N. Vander-Zanden, and D. Gajski, “MILO: A Microarchitecture and Logic Optimization System,” in VLSI Design Environments, (G. W. Zobrist, editor), G & B Science Publishers, 2000, pp. 265-299.
E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, “Strategically Programmable Systems,” The Computer Engineering Handbook, CRC Press, December 2001.
A. Rettberg, F. Rammig, A. Gerstlauer, D. D. Gajski, W. Hardt, and B. Kleinjohann, “The Specification Language SpecC within the PARADISE Design Environment,” Architecture and Design of Distributed Embedded Systems, edited by B. Kleinjohann, Kluwer Academic Publishers, April 2001.
X. Yang, E. Bozorgzadeh, M. Sarrafzadeh, and M. Wang, “Modern Standard-cell Placement Techniques.” Layout Optimization in VLSI Design, Kluwer Academic Publishers, 2002.
P. Panda and N. Dutt, “Memory Architectures for Embedded Systems-on-Chip,” Lecture Notes in Computer Science ( LNCS ) Vol. 2552, Springer-Verlag, 2002, pp. 647-662.
P. Mishra and N.D. Dutt, “Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions,” Design and Analysis of Distributed Embedded Systems, Bernd Kleinjohann et al., Editors, Kluwer Academic Publishers, 2002, pp. 81-90.
L. Cai, M. Olivarez, and D. Gajski, “The Guidelines and JPEG Encoder Study Case of Systems Level Architecture Exploration Using SpecC Methodology,” in System On Chip Design Languages(Mignotte, Villar, Horobin, eds.), Kluwer Academic Publishers, 2002.
E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, “Optimization for Reconfigurable Systems Using Hierarchical Abstraction,” J. Cong and J. R. Shinnerl (Editors).Multilevel Optimization and VLSI CAD. Kluwer Academic Publishers, Boston, 2002.
X. Yang, E. Bozorgzadeh, M. Sarrafzadeh, and M. Wang, “Modern Standard-cell Placement Techniques”. Layout Optimization in VLSI Design, Kluwer Academic Publishers, 2002.
A. Gerstlauer, H. Yu and D. D. Gajski, “RTOS Modeling for System-Level Design,” Embedded Software for SoC, edited by A. A. Jerraya, S. Yoo, N. When, D. Verkest, Kluwer Academic Publishers, June 2003.