D. Gajski, "Introduction: System Level Design: Past, Present and Future", Lauwereins, Rudy; Madsen, Jan (Editors) Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Springer, ISBN: 978-1-4020-6487-6, March 2008

B. Gorjiara, M. Reshadi, D. Gajski, "Low-Power Design with NISC Technology", J. Henkel, S. Parameswaran, Designing Embedded Processors: A Low Power Perspective, Springer, ISBN: 978-1-4020-5868-4, April 2007.

E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, "Optimization for Reconfigurable Systems Using Hierarchical Abstraction," J. Cong and J. R. Shinnerl (Editors). Multilevel Optimization and VLSI CAD. Kluwer Academic Publishers, Boston, 2002.

E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, "Strategically Programmable Systems," The Computer Engineering Handbook, CRC Press, December 2001. 

L. Cai, M. Olivarez, and D. Gajski, "The Guidelines and JPEG Encoder Study Case of Systems Level Architecture Exploration Using SpecC Methodology," in System On Chip Design Languages (Mignotte, Villar, Horobin, eds.), Kluwer Academic Publishers, 2002.

P. Mishra and N.D. Dutt, "Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions," Design and Analysis of Distributed Embedded Systems, Bernd Kleinjohann et al., Editors, Kluwer Academic Publishers, 2002, pp. 81-90.

P. Panda and N. Dutt, "Memory Architectures for Embedded Systems-on-Chip," Lecture Notes in Computer Science ( LNCS ) Vol. 2552, Springer-Verlag, 2002, pp. 647-662.

N. Vander-Zanden, and D. Gajski, "MILO: A Microarchitecture and Logic Optimization System," in VLSI Design Environments, (G. W. Zobrist, editor), G & B Science Publishers, 2000, pp. 265-299.

X. Yang, E. Bozorgzadeh, M. Sarrafzadeh, and M. Wang, "Modern Standard-cell Placement Techniques." Layout Optimization in VLSI Design, Kluwer Academic Publishers, 2002.