To overcome the complexities in today's System-on-Chip (SoC) design, researchers have developed sophisticated design environments that significantly reduce design and development time through automation. Typically, a SoC design is specified in a system-level description language (SLDL) at a high abstraction level, called a specification model. This model is then step-wise refined down to an implementation with the help of automated (or semi-automated) synthesis tools.

While much research has focused on SoC synthesis tools, little has been done to support the designer in coming up with the initial specification model. In fact, studies on industrial-size examples (MP3 decoder, GSM vocoder, ...) have shown that even in the presence of algorithms given in C code, 90% of the system design time is spent on coding and re-coding of the specification model in SLDL. Moreover, the quality of the golden specification model has tremendous impact on the cost and quality of the resulting system implementation. Thus, creating and optimizing the specification model is a critical task towards successful SoC design.

It is the goal of this research project to:

• identify tasks in system specification and re-coding which are suitable for automation
• design and develop prototype tools for
  • specification generation
  • automated re-coding
  • source code optimization
• demonstrate the benefits using real-life examples

FAT: Fast and Accurate Transaction-Level Modeling
Key Researcher: Gunar Schirner

The field of embedded systems increasingly extends to more complex scenarios including safety critical systems. Distributed embedded real-time systems with many processors become necessary. Accurate communication modeling is an important issue for the design of those complex systems. However, efficient system level design requires also high execution performance especially for communication models.

Recent research work introduced Transaction Level Modeling as a means of increasing the simulation performance. Here, large speed-up is gained by abstracting away communication details. Inevitably this results in a loss of simulation accuracy. However, due to the complexity of accuracy measurements and its statistical analysis, no clear expressive quantification of the speed-accuracy tradeoff prevails.

The goals of this research project include:

• identification of appropriate performance and accuracy properties for communication models
• definition and statistical analysis of accuracy measurements
• development and definition of modeling styles that yield high execution speed yet maintain required accuracy
• demonstration of benefits using industry bus standards (e.g. AMBA, CAN)

SpecC Reference Compiler
Key Researcher: Pramod Chandraiah
Web Site: http://www.ics.uci.edu/~specc/reference/

The SpecC Reference Compiler (SCRC) is an Open Source implementation of a compiler and simulator for the SpecC language.

The goal of the SpecC Reference Compiler is to:

• promote SpecC standardization
• provide a reference implementation, that is
  • compliant with the SpecC Language Reference Manual (LRM V2.0)
  • freely available
• provide a basis for SpecC tool development

The SCRC distribution consists of:

• a SpecC compiler (parser, internal representation, code generator)
• a SpecC simulator (run-time libraries for SpecC execution)
• a SpecC standard channel library (channels for synchronization, etc.)
• a test suite (SpecC LRM compliance test cases)

Reference:
R. Doemer, A. Gerstlauer, and D. Gajski, "SpecC Language Reference Manual, Version 2.0," December 12, 2002 .
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