PhD Final Defense by Zhiming Cheng

Location: 2111 Engineering Hall Date and Time: March 8th, 2012, 2:00-3:30PM Committee: Professor Payam Heydari (Chair) Professor Michael Green Professor Peter Burke Title: Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging Abstract: Silicon technology, with its superior integration capability and low cost, has changed the world dramatically during the past few decades and recently has entered the realm of millimeter-wave (MMW) system design that is used to be dominated by III-V compound semiconductor technologies. Benefiting from the continuous feature size scaling of silicon technology, passive MMW imagers could be built on chip which paves the way for developing low-cost, compact wafer-scale imagers. This dissertation focuses on the design of fully integrated W-band passive imager and also covers the design of W-band synthesizer which is one of the most critical and challenging building blocks of the imaging receiver. Two chips for 96GHz frequency generation incorporating the same Ka-band PLL and (1) an injection-locked frequency tripler (ILFT); (2) a harmonic-based frequency tripler (HBFT) in 0.18?m SiGe BiCMOS (fT/fmax=200/180GHz) are presented. The ILFT and HBFT preceded by the same Ka-band PPL achieve measured closed-loop phase noise of -93dBc/Hz and -92dBc/Hz at 1MHz offset, respectively. Both chips are designed under the same power consumption of 14mW from 1.8V/2.5V supplies. This work presents the first implementation of an injection-locked-based frequency multiplier in SiGe BiCMOS process. W-band transformer-based injection-locked frequency tripler (T-ILFT) is also designed and implemented in 65nm standard CMOS technology using a 0.8V supply voltage. THe use of injection locking topology with on-chip transformer provides several advantages over conventional design. A fully integrated W-band 2×2 focal-plane array (FPA) for passive millimeter-wave imaging is demonstrated in 0.18?m SiGe BiCMOS process. The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture with an on-chip slot folded dipole antenna. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. This imaging receiver (without antenna) achievers a measured average responsivity and noise equivalent power of 285MV/W and 8.1fW/Hz1/2, respectively, across the 86-106GHz bandwidth, which results a calculated NETD of 0.48K with a 30ms integration time. The system NETD increases to 3K with on-chip antenna due to its low efficiency at W-band. This work demonstrates the highest integration level of any silicon-based systems in the 94GHz imaging band.