Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures
by Amir Hossein Gholamipour

Committee:
Prof. Fadi Kurdahi (chair)
Prof. Ahmed Eltawil
Prof. Michael Dillencourt

An increasing number of digital systems, from wireless devices to multi-media terminals, are characterized by their multi-mode operation. This refers to the ability of a system to modify its characteristics or behavior based on user inputs or changes in the operational environment. FIR filters are frequently used in the operation of multi-mode systems due to their inherent stability and linear phase. In majority of such systems implementing a multi-mode FIR filter is the challenge in realizing the multi-mode behavior. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). To implement multi-mode FIR filters, General Purpose processors are incompetent in delivering the performance while Application Specific Integrated Circuits (ASICs) do not support the required flexibility. On Partially reconfigurable FPGA platforms we can optimize a filter structure based on the fixed parameters of filter and change the mode of operation by reconfiguring the fabric. However the reconfiguration overhead in this approach is not negligible.

In this work we introduce an approach which produces a spectrum of filter designs which trade-off area for reconfiguration overhead. In this thesis I prove that the problem of filter optimization can be solved in polynomial time. Furthermore as filter designs in the sequence of reconfiguration have similarities in their parameter sets, we propose to jointly optimize their designs to further reduce the reconfiguration overhead. We consider the physical limitations of implementing multi-mode filters on FPGAs and propose a placement-aware approach to account for those limitations. Our placement-aware approach is an additional step called /Mapping/ that is introduced before floorplanning the design. In my work, I show that mapping is an NP-hard problem and I propose ILP formulation and heuristics to solve it. As the result of my research, I have developed a tool which gets the description of a sequence of filters as an input and generates the RTL design of the filters in VHDL code. It then gives hints on how to map the modules of the design to physical regions on the FPGA chip. This design approach has been tested on a rich set of applications including “preamble detection” unit of OFDMA receivers, template matching and matched-filter based spectrum sensors. The results show the importance of this approach and the efficiency of the solutions proposed.