Enix: A Lightweight Dynamic Operating System for Tightly Constrained Wireless Sensor Platforms
Release Date: November 3, 2010
Download pdf: Enix: A Lightweight Dynamic Operating System for Tightly Constrained Wireless Sensor Platforms
Enix is a lightweight dynamic operating system for tightly constrained platforms for wireless sensor networks (WSN). Enix provides a cooperative threading model, which is applicable to event-based WSN applications with little run-time overhead. Virtual memory is supported with the assistance of the compiler, so that the sensor platforms can execute code larger than the physical code memory they have. To enable firmware update for deployed sensor nodes, Enix supports remote reprogramming. The commonly used library and the main logical structure are separated; each sensor device has a copy of the dynamic loading library in the Micro-SD card, and therefore only the main function and user-defined subroutines should be updated through RF. A lightweight, efficient
file system named EcoFS is also included in Enix. The code size and data size of Enix with full-function including EcoFS are 8 KB and 512 bytes, respectively, enabling Enix to run on many RF-enabled systems-on-chip that cannot run most other WSN OSs.
EcoExec: An Interactive Execution Framework for Ultra Compact Wireless Sensor Nodes
Release Date: June 21, 2010
Download pdf: EcoExec: An Interactive Execution Framework for Ultra Compact Wireless Sensor Nodes
EcoExec is a host-assisted interactive execution environment for wireless sensing systems. Users can interact with sensor nodes by viewing attributes and invoking functions via a command-line interface. Functions that are not resident in the node’s firmware are automatically compiled on the host, packaged up and downloaded to the node, linked, and executed, all seamlessly and transparently to the user. By packaging these features in a dynamically object-oriented programming environment such as Python, EcoExec enables programmers to experiment with features of the wireless sensor nodes and to rapidly develop application software. Most importantly, EcoExec empowers resource-constrained wireless sensor platforms with rich functionalities that would otherwise be prohibitive, thanks to its host-assisted execution feature with code swapping over the network. Experimental results on actual wireless sensor platforms show EcoExec to perform effectively with negligible observed overhead to the user.
Release Date: May 2008 (NISC Toolset 2008.05)
NISC Demo: http://www.cecs.uci.edu/~nisc/
No-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis.
With NISC Technology, you can simultaneously gain higher productivity and better quality of results. Other techniques only offer one of these benefits.
Two popular approaches for designing digital systems:
- Low-level design at Register Transfer Level (RTL).
- Can lead to efficient IPs but the development time and cost is very high.
- High-Level-Synthesis (HLS) goal: improve productivity
- Automatically converts high-level description of the IP (e.g. written in C language) to RTL
- Designer has little control over the quality of the generated RTL in terms of clock frequency, area, manufacturability, power, etc
- Result quality typically bad.
- High-level design using general-purpose or custom processors.
- Development time and cost is much lower, but the efficiency and implementation quality is also much lower.
- Application-Specific-Instruction-Processors (ASIP) goal: improve quality
- Adds application-specific instructions to the processor
- Finding suitable custom instructions and adding them to the toolset (compiler, simulator, etc.) is a very challenging task.
- Because of their instruction-set, processors (including ASIPs) impose a minimum overhead in terms of area, power, and performance.
- The processor-based implementation may become more appealing only when the IP design complexity is above a certain level (relatively very high).
- Not suitable if you want to run a few algorithms or design a hardware block
D. Gajski, “NISC: The Ultimate Reconfigurable Component,” TR 03-28, October 1, 2003.
ESE: Embedded System Environment
Release Date: March 28, 2008
Web Site: http://www.cecs.uci.edu/~ese/
ESE is a toolset for modeling, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End.
ESE Front End provides automatic generation of SystemC transaction level models (TLMs) from graphical capture of system platform and application C/C++ code. ESE generated TLMs can be used either as virtual platforms for SW development or for fast and early timing estimation of system performance. The retargetable performance estimation utilizes the LLVM infrastructure.
ESE Back End provides automatic synthesis from TLM to Pin-Cycle Accurate Model (PCAM) consisting of RTL interfaces, system SW and prototype ready FPGA project files. ESE generated RTL can be synthesized using standard logic synthesis tools and system SW can be compiled along with application code for a given processor. ESE automatically creates Xilinx EDK projects for download to Xilinx boards.
The key advantages of ESE are huge productivity gain (provided by model automation and higher design abstraction) and ease of use for non-experts (provided by C-based and graphical design input). To learn more about ESE or to download ESE Front End, please visit the ESE Web Site.
D. Gajski, A. Gerstlauer, and S. Abdi, “Embedded System Design: Concepts and Tools,” ASP-DAC 2007 Pacifico Yokohama, Yokohama, Japan, January 23, 2007.
SpecC Reference Compiler
Release Date: September 28, 2006 (version 2.1)
Web Site: http://www.cecs.uci.edu/~specc/
The SpecC Reference Compiler (SCRC) is an Open Source implementation of a compiler and simulator for the SpecC language.
The goal of the SpecC Reference Compiler is to:
- promote SpecC standardization
- provide a reference implementation, that is
- compliant with the SpecC Language Reference Manual (LRM V2.0)
- freely available
- provide a basis for SpecC tool development
The SCRC distribution consists of:
- a SpecC compiler (parser, internal representation, code generator)
- a SpecC simulator (run-time libraries for SpecC execution)
- a SpecC standard channel library (channels for synchronization, etc.)
- a test suite (SpecC LRM compliance test cases)
R. Doemer, A. Gerstlauer, and D. Gajski, “SpecC Language Reference Manual, Version 2.0,” December 12, 2002 .
B#: A Battery Emulator and Power-Profiling Instrument
Release Date: March, 2005
Download pdf: http://www.ece.uci.edu/~chou/battDT-layout.pdf
B# (B sharp) is a programmable power supply that emulates battery behavior. It measures current load, calls a battery simulation program to compute voltage in real time, and controls a linear regulator to mimic a battery’s voltage output. The instrument enables validation of battery-aware power optimization techniques with accurate, controllable, reproducible results.
Release Date: September 19, 2003
Web Site: http://www.cecs.uci.edu/~spark/
SPARK is a C-to-VHDL high-level synthesis framework that employs a set of innovative compiler, parallelizing compiler, and synthesis transformations to improve the quality of high-level synthesis results. The compiler transformations have been re-instrumented for synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models. The SPARK methodology is particularly targeted to control-intensive microprocessor functional blocks and multimedia and image processing applications. We have validated the effectiveness of our approach and evaluated the various optimizations for large real-life applications such as the Instruction Length Decoder from the Intel Pentium and multimedia applications such as MPEG-1, MPEG-2 and the GIMP image processing tool.
R. Goering, “Tool promises parallelizing synthesis,” EE Times, December 19, 2003
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