Seminars by CECS

PhD Defense: Data -Driven Modeling and Analysis for Trustworthy Cyber-Physical Systems

Name: Sina Faezi

Chair: Dr. Mohammad Al Faruque

Date: April 21, 2021

Time: 10:00 AM

Location: Zoom

Committee: Dr. Mohammad Al Faruque (UCI), Dr. Philip Brisk (UCR), Dr. Zhou Li (UCI)

Title: “Data-Driven Modeling and Analysis for Trustworthy Cyber-Physical Systems”

Abstract:

In the age of digitization, a layer of cyber software sits on a hardware circuit and controls the physical systems around us. The tight integration of cyber and physical components is referred to as Cyber-Physical Systems (CPS). The interaction between cyber and physical components brings unique challenges which traditional modeling tools struggle to resolve. Particularly, they often fail to model the unintentional physical manifestation of cyber-domain information flows (side-channel signals) which may result in trust issues in the system.

In this thesis, we take a data-driven approach to model a CPS behavior when it is exposed to various information flows. First, we demonstrate how it is possible to extract valuable cyber-domain information by recording the acoustic noise generated by a DNA synthesizer. Then, we consider an integrated circuit as a CPS by itself and monitor the chip through electromagnetic and power side-channels to detect hardware Trojans (HT) in the chip.

HT is a malicious modification of the hardware implementation of a circuit design which may lead to various security issues over the life-cycle of a chip. One of the major challenges for HT detection is its reliance on a trusted reference chip (a.k.a golden chip). However, in practice, manufacturing a golden chip is costly and often considered infeasible.  This thesis investigates a creative neural network  design and training methodology which eliminates the need for a golden chip. Furthermore, it proposes using hierarchical temporal memory (HTM) as a data driven approach which can be updated over the chip’s life-cycle and uses that for run-time HT detection.

Bio: Sina Faezi is a Ph.D. candidate in computer engineering at the University of California, Irvine (UCI).  He works under Professor M. Al Faruque in the Autonomous and Intelligent Cyber-Physical Systems (AICPS) laboratory on the topic of data-driven modeling and analysis for Cyber-Physical systems. He creates data-driven models and then uses them to tackle practical issues like durability, security, process control, etc., in cyber-physical systems.  Through his Ph.D.,  he has published numerous articles in prestigious conferences and has received Broadcom Foundation Graduate Engineering fellowship. He has completed his B.Sc. in electrical engineering at the Sharif University of Technology in 2015 and has received his M.S. degree in computer engineer from UCI in 2017.

 

 
PhD Defense: Programmable Accelerators for Lattice-based Cryptography

Name: Hamid Nejatollahi

Advisor: Nikil Dutt

Date: June 11, 2020

Time: 10:00 AM

Committee: Ian Harris, Rainer Doemer

Thesis: “Programmable Accelerators for Lattice-based Cryptography”

Abstract:

Advances in computing steadily erode computer security at its foundation, calling for fundamental innovations to strengthen the weakening cryptographic primitives and security protocols.  While many alternatives have been proposed for symmetric key cryptography and related protocols (e.g., lightweight ciphers and authenticated encryption), the alternatives for public-key cryptography are limited to post-quantum cryptography primitives and their protocols. In particular, lattice-based cryptography is a promising candidate, both in terms of foundational properties, as well as its application to traditional security problems such as key exchange, digital signature, and encryption/decryption.  At the same time, the emergence of new computing paradigms, such as Cloud Computing and Internet of Everything, demand that innovations in security extend beyond their foundational aspects, to the actual design and deployment of these primitives and protocols while satisfying emerging design constraints such as latency, compactness, energy efficiency, and agility. In this thesis, we propose a methodology to design programmable hardware accelerators for lattice-based algorithms and we use the proposed methodology to implement flexible and energy-efficient post-quantum cache- and DMA-based accelerators for the most promising submissions to the  NIST  standardization contest.   We validate our methodology by integrating our accelerators into an HLS-based SoC infrastructure based on the X86 processor and evaluate overall performance.  In addition, we adopt the systolic architecture to accelerate the polynomial multiplication, which is the heart of a subset of LBC algorithms (i.e., ideal LBC), on the field-programmable gate arrays (FPGAs).  Finally, we propose a high-throughput Processing In-Memory (PIM) accelerator for the number-theoretic transform (NTT-) based polynomial multiplier.

 

 
PhD Defense: Security Modeling and Analysis for Emerging Intelligent Transportation Systems

Name: Anthony Lopez

Chair: Dr. Mohammad Al Faruque

Date: December 4, 2020

Time: 3:00PM – 5:00PM

Location: Zoom

Committee: Dr. Mohammad Al Faruque (Chair), Dr. Wenlong Jin and Dr. Zhou Li

Title: “Security Modeling and Analysis for Emerging Intelligent Transportation Systems”

Abstract:

Massive deployment of embedded systems including various sensors, on-board and road-side computing units, wireless communication among vehicles and infrastructure via enabling technology of the Internet of Things (IoT), and intelligent algorithms are changing the transportation sector, leading to novel systems known as Intelligent Transportation Systems (ITS). However, with these newer technologies come unforeseen safety and security concerns. In spite of the recent interest and importance of ITS security, there have been few efforts to consolidate, structure, and unify this large body of research. There has also been an increasing divergence between academic research and industrial practice in the area, each of which has evolved independently with little interaction and in some cases with little understanding of the assumptions, issues,  trade-offs, and scales considered by the other. In addition to a lack of a clear consolidation and summary of related ITS security works, research on modeling/analysis tools for ITS security is also lacking.

For these reasons, this dissertation tackles these challenges by providing 1) a consolidation in ITS security research in terms of both V2X and IoT aspects (with a focus on battery systems) and 2) two methodologies to model and analyze the performance of ITS under attacks. Both methodologies are designed to be standalone open-sourced tools that ITS designers, engineers, and researchers may utilize to promote the growth of ITS security The first methodology focuses on modeling attacks and analyzing their impacts on vulnerable connected Fixed-Time Traffic Signal Control Systems. The second methodology is presented hand-in-hand with an attack taxonomy that focuses on a more advanced ITS system use-case called Vehicular Communication (V2X) Advisory Speed Limit Control (ASL) and involves the study of various attack types on different components of the ITS.

Bio: Anthony Lopez is a Ph.D. student studying Computer Engineering at the University of California Irvine (UCI), USA in the Embedded and Cyber-Physical Systems Lab under Professor Mohammad Al Faruque. He earned a B.S. from UC San Diego, USA and an M.S. from UC Irvine, both in Computer Engineering. His research focuses on the secure design, modeling, analysis and simulation of cyber-physical transportation systems. He is an IEEE student member and an NSF Graduate Research Fellowship Program awardee.

 

 
PhD Defense: Approximate and Bit-width Con gurable Arithmetic Logic Unit Design for Deep Learning Accelerator

Name: Xiaoliang Chen

Chair: Prof. Fadi Kurdahi

Date: June 2, 2020

Time: 10:00 AM

Location: Zoom

Committee: Prof. Fadi J. Kurdahi (Chair), Prof. Ahmed M. Eltawil and Prof. Rainer Doemer

Title: “Approximate and Bit-width Con gurable Arithmetic Logic Unit Design for Deep Learning Accelerator”

Abstract:

As key building blocks for digital signal processing, image processing and deep learning etc, adders, multi-operand adders and multiply-accumulator units (MAC) have drawn lots of attention recently. Two popular ways to improve arithmetic logic unit (ALU) performance and energy efficiency are approximate computing and precision scalable design. Approximate computing helps achieve better performance or energy efficiency by trading accuracy. Precision scalable design provides the capability of allocating just-enough hardware resources to meet the application requirements.

In this thesis, we first present a correlation aware predictor (CAP) based approximate adder, which utilizes spatial-temporal correlation information of input streams to predict carry-in signals for sub-block adders. CAP uses less prediction bits to reduce the overall adder delay. For highly correlated input streams, we found that CAP can reduce adder delay by ~23.33% and save ~15.9% area at the same error rate compared to prior works.

Inspired by the success of approximate multipliers using approximate compressors, we proposed a pipelined approximate compressor based speculative multi-operand adder (AC-MOA). All compressors are replaced with approximate ones to reduce the overall delay of the bit-array reduction tree. An efficient error detection and correction block is designed to compensate the errors with one extra cycle. Experimental results showed the proposed 8-bit 8-operand AC-MOA achieved 1.47X ~ 1.66X speedup over conventional baseline design.

Recent research works on deep learning algorithms showed that bit-width can be reduced without losing accuracy. To benefit from the fact that bit-width requirement varies across deep learning applications, bit-width configurable designs can be used to improve hardware efficiency. In this thesis a bit-width con gurable MAC (BC-MAC) is proposed. BC-MAC uses a spatial-temporal approach to support variable precision requirements for both activations and weights. The basic processing element (PE) of BC-MAC is a multi-operand adder. Multiple multi-operand adders can be combined together to support input operands of any precision. Bit-serial summation is used to accumulate partial addition results to perform MAC operations. Booth encoding is employed to further boost the throughput. Synthesis results on TSMC 16nm technology and simulation results show the proposed MAC achieves higher area efficiency and energy efficiency than the state-of-the-art designs, making it a promising ALU for deep learning accelerators.

 
PhD Defense: Advancing Compiler and Simulator Techniques for Highly Parallel Simulation of Embedded Systems

Name: Zhongqi Cheng

Chair: Prof. Rainer Doemer

Date: May 29th, 2020

Time: 02:00 PM

Location:  Zoom

Committee: Rainer Doemer (Chair), Prof. Mohammad Al Faruque and Prof. Aparna Chandramowlishwaran

Title: “Advancing Compiler and Simulator Techniques for Highly Parallel Simulation of Embedded Systems”

Abstract:

As an Electronic System Level (ESL) design language, the IEEE SystemC standard is widely used for testing, validation and verification of embedded system models. Discrete Event Simulation (DES) has been used for decades as the default SystemC simulation semantic. However, due to the sequential nature of DES, Parallel DES has recently gained an increasing amount of attention for performing high speed simulations on parallel computing platforms. To further exploit the parallel computation power of modern multi- and many-core platforms, Out-of-order Parallel Discrete Event Simulation (OoO PDES) has been proposed. In OoO PDES, threads comply with a partial order such that different simulation threads may run in different time cycles to increase the parallelism of execution. The Recoding Infrastructure for SystemC (RISC) has been introduced as a tool flow to fully support OoO PDES.

To preserve the SystemC semantics under OoO PDES, a compiler based approach statically analyzes the race conditions in the input model. However, there are severe restrictions: the source code for the input design must be available in one file, which does not scale. This disables the use of Intellectual Property (IP) and hierarchical file structures. In this dissertation, we propose a partial-graph based approach to scale the static analysis to support separate files and IP reuse. Specifically, the Partial Segment Graph (PSG) data structure is proposed and is used to abstract the behaviours and communication of modules within a single translation unit. These partial graphs are combined at top level to reconstruct the complete behaviors and communication of the entire model.

We also propose new algorithms to support the static analysis for modern SystemC TLM-2.0 standard. SystemC TLM-2.0 is widely used in industrial ESL designs for better interoperability and higher simulation speed. However, it is identified as an obstacle for parallel SystemC simulation due to the disappearance of channels. To solve the problem, we propose a compile time approach to statically analyze potential conflicts among threads in SystemC TLM-2.0 loosely- and approximately-timed models. A new Socket Call Path (SCP) technique is introduced which provides the compiler with socket binding information for precise static analysis. Based on SCP, an algorithm is proposed to analyze entangled variable pairs for automatic and accurate conflict analysis.

Besides the works on the compiler side, we focus as well on increasing the simulation speed of OoO PDES. We observe that the granularity of the Segment Graph (SG) data structure used in static analysis has a high impact on OoO PDES. This motivates us to propose a set of coding guidelines for the RISC users to properly refine their SystemC model for a higher simulation speed.

Furthermore, in this dissertation, an algorithm is proposed to optimize directly the event delivery strategy in OoO PDES. Event delivery in OoO PDES was very conservative, which often postponed the execution of waiting threads due to unknown future behaviors of the SystemC model, and in turn became a bottleneck of simulation speed. The algorithm we propose takes advantage of the prediction of future thread behaviors, and therefore allows waiting threads to resume execution earlier, resulting in significantly increased simulation speed.

To summarize, the contributions of this dissertation include: 1) a scalable RISC tool flow for statically analyzing and protecting 3rd party IPs in models with multiple files, 2) an advanced static analysis approach for modern SystemC TLM-2.0 models, 3) a set of coding guidelines for RISC users to achieve higher simulation speed, and 4) a more efficient event delivery algorithm in OoO PDES scheduler using prediction information.

Together, these compiler and simulator advances enable OoO PDES for larger and modern model simulation and thus improve the design of embedded systems significantly, leading to better devices at lower cost in the end.

 
PhD Defense: Design and Implementation of Robust Full-Duplex Wireless Network

Name: Sergey Shaboyan

Chair: Prof. Ahmed Eltawil

Date: March 10th, 2020

Time: 09:30 AM

Location:  EH 3206

Committee: Prof. Ahmed Eltawil (Chair), Prof. Ender Ayanoglu, Prof. Zhiying Wang

Title: “Design and Implementation of Robust Full-Duplex Wireless Network”

Abstract:

Recently Full-Duplex (FD) communication has gained significant interest due to demonstrable increase in throughput and spectral efficiency. Conventional Half-duplex (HD) communication systems use either time-duplexing or frequency-duplexing to avoid self-interference. In contrast, full-duplex systems transmit and receive simultaneously on the same frequency band, thus optimally utilizing available resources. The main challenge in FD systems is managing the self-interference (SI) signal at each node, which is typically orders of magnitude larger than the intended signal of interest (SOI). To achieve sufficient SI suppression, FD systems rely on cancellation across multiple domains such as spatial, analog, and digital. However, number of practical, FD specific challenges arise impacting quality of service, when at least one node in a network operates in full-duplex mode.

In this thesis, we consider practical issues of wireless networks containing a full-duplex node. The ultimate goal of this work is to design and implement real-time, end-to-end networks consisting of at least one FD node that is capable of improving network performance under limited available bandwidth constraint. First, we identify synchronization issues in a network consisting of a full-duplex base station communicating with half-duplex nodes. Novel synchronization techniques specific for full-duplex networks are proposed that allow compensation of synchronization errors in time and frequency. The proposed techniques are implemented and tested experimentally on a real-time full-duplex wireless network. Second, we characterize the dynamic environment impact on the received self-interference in the FD system, which is equipped with a reconfigurable antenna as a passive SI suppression mechanism. The self-interference channel delay profile is measured using the FD system operating on 5MHz, 10MHz, and 20MHz bandwidths. The measured channel profiles collected under suppressing and non-suppressing antenna patterns are compared, and channel changes in static, as well as dynamic environments, are highlighted. We then statistically model the SI channel by performing probability distribution fitting to SI channel data. Third, the thesis proposes a Wi-Fi compliant self-interference active cancellation technique for amplify and forward, as well as decode and forward full-duplex relays. Finally, we design and implement an end-to-end wireless network extended with the aid of a custom-designed amplify and forward full-duplex relay. We then analyze the relay coverage limitation under the stability and transmit power constraints. The network performance is analyzed as a function of relay location for constant gain and constant transmit power modes, consequently suggesting optimal relay location that will maximize signal to noise plus interference ratio (SINR) at the destination node. We evaluate the overall network performance by simulation, as well as experimentally in outdoor/indoor environments.

 
PhD Defense: Novel Monitoring, Detection, and Optimization Techniques for Neurological Disorders

Name: Seyede Mahya Safavi

Chair: Prof. Pai Chou

Date: February 20th, 2020

Time: 10:00 AM

Location:  EH 3404

Committee: Prof. Pai Chou (Chair), Prof. Beth Lopour, Prof. Phillip Sheu

Title: “Novel Monitoring, Detection, and Optimization Techniques for Neurological Disorders”

Abstract:

The advancement in chronically implanted neural recording devices has led to advent of assisting devices for rehabilitation and restoring lost sensorimotor functions in patients suffering from paralysis. Electrocorticogram (ECoG) signal can record high-Gamma sub-band activity known to be related to hand movements. In the first part of this work, we Propose a finger movement detection technique based on ECoG source localization. In fact, the finger flexion and extension are originating in slightly different areas of motor cortex. The origin of the brain activity is used as the distinctive feature for decoding the finger movement.

The real-time implementation of brain source localization is challenging due to extensive iterations in the existing solutions. In the second part of this work, we have proposed two techniques to reduce the computational complexity of the Multiple Signal Classification (MUSIC) algorithm. First the cortex surface is parsed into several regions. Next, a novel nominating procedure will pick a number of regions to be searched for brain activity. In the second step, an electrode selection technique based on the Cramer-Rao bound of the errors is proposed to select the best set of an arbitrary number of electrodes. The proposed techniques lead to 90% reduction in computational complexity while maintaining a good concordance in terms of localization error compared to regular MUSIC algorithm.

Epilepsy is a neurological disorder with multiple comorbid conditions including cardiovascular and respiratory disorders. The cardiovascular imbalance is of great importance since the mechanisms of Sudden Unexpected Death in Epilepsy (SUDEP) is still unknown. The ictal tachycardia is the most well-known cardiac imbalance during the seizure. In the third part of this dissertation, we used an optical sensor called photoplethysmogram (PPG) to investigate the variations in ictal blood flow in limbs. Six different features related to hemodynamics were derived from PPG pulse morphology. A consistent pattern of ictal change was observed across all the subjects/seizures. These variations suggest an increase in vascular resistance due to an increase in sympathetic tone. The timing analysis of the PPG features revealed some PPG feature variations can precede the ictal tachycardia by 50 seconds. These features were used to train a neural network based on Long Short Term Memory LSTM architecture for automatic seizure detection. We were able to reduce the False Alarm rate by 50% compared to other heart rate variability based detectors.

 
PhD Defense: Efficient Offline and Online Training of Memristive Neuromorphic Hardware

Name: Mohammed Fouda

Chair: Prof. Ahmed Eltawil

Date: February 6th, 2020

Time: 9:30 AM

Location:  EH 3206

Committee: Ahmed Eltawil (Chair), Prof. Fadi Kurdahi, Prof. Nikil Dutt, Prof. Emre Neftci

Title: “Efficient Offline and Online Training of Memristive Neuromorphic Hardware”

Abstract:

Brain-inspired neuromorphic systems have witnessed rapid development over the last decade from both algorithmic and hardware perspectives. Neuromorphic hardware promises to be more energy- and speed- efficient as compared to traditional Von-Neumann architectures. Thanks to the recent progress in solid-state devices, different nanoscale-nonvolatile memory devices, such as RRAMs (memristors), STT-RAM and PCM, support computations based on mimicking biological synaptic response. The most important advantage of these devices is their ability to be sandwiched between interconnect wires creating crossbar array structures that are inherently able to perform matrix-vector multiplication (MVM) in one step. Despite the great potential of RRAMs, they suffer from numerous nonidealities limiting the performance, including, high variability, asymmetric and nonlinear weight update, endurance, retention and stuck at fault (SAF) defects in addition to the interconnect wire resistance that creates sneak paths. This thesis will focus on the application of RRAMs for neuromorphic computation while accounting for the impact of device nonidealities on neuromorphic hardware.

In this thesis, we propose software-level solutions to mitigate the impact of nonidealities, that highly affect the offline (ex-situ) training, without incorporating expensive SPICE or numerical simulations. We propose two techniques to incorporate the effect of sneak path problem during training, in addition to the device’s variability, with negligible overhead. The first technique is inspired by the impact of the sneak path problem on the stored weights (devices’ conductances) which we referred to as the mask technique. This mask is element-wise multiplied by the weights during the training. This mask can be obtained from measured weights of fabricated hardware. The other solution is a neural network estimator which is trained by our SPICE-like simulator. The test validation results, done through our SPICE-like framework, show significant improvement in performance, close to the baseline BNNs and QNNs, which demonstrates the efficiency of the proposed methods. Both techniques show the high ability to capture the problem for multilayer perceptron networks for MNIST dataset with negligible runtime overhead. In addition, the proposed neural estimator outperforms the mask technique for challenging datasets such as CIFAR10. Furthermore, other nonidealities such as SAF defects and retention are evaluated.

We also develop a model to incorporate the stochastic asymmetric nonlinear weight update in online (in-situ) training. We propose two solutions for this problem; 1) a compensation technique which is tested on a small scale problem to separate two Laplacian mixed sources using online independent component analysis. 2) stochastic rounding and is tested on a spiking neural network with deep local learning dynamics showing only a 1~2\% drop in the baseline accuracy for three different RRAM devices. We also propose Error-triggered learning to overcome the limited endurance problem with only 0.3% and 3% drop in the accuracy for N-MNIST and DVSGesture datasets with around 33X and 100X reduction in the number of writes, respectively.

Finally, the prospects of this neuromorphic hardware are discussed to develop new algorithms with the existing resistive crossbar hardware including its nonidealities.

 
PhD Defense: Towards Engineering Computer Vision Systems: From Web to FPGAs

Final Defense – Sajjad Taheri

Date: August 26, 2019

Time: 2:00 pm

Location: Donald Bren Hall 4011

Committee: Alex Nicolau(chair), Alex Veidenbaum(co-chair), Nikil Dutt

Title: Towards Engineering Computer Vision Systems: From Web to FPGAs
Abstract:
Computer vision has many applications that impact our daily lives, such as automation, entertainment, healthcare, etc. However, computer vision is very challenging. This is in part due to intrinsically difficult nature of the problem and partly due to the complexity and size of visual data that need to be processed. To be able to deploy computer vision in many practical use cases, sophisticated algorithms and efficient implementations are required. In this dissertation, we consider two platforms that are suitable for computer vision processing, yet they were not easily accessible to algorithm designers and developers: The Web and FPGA-based Accelerators. Through the development of open-source software, we highlight challenges associated with vision development on each platform and demonstrate opportunities to mitigate them.
The Web is the world’s most ubiquitous computing platform which hosts a plethora of visual content. Due to historical reasons such as insufficient JavaScript performance and lack of API support for acquiring and manipulating images, computer vision is not mainstream on the Web. We show that in light of recent web developments such as vastly improved JavaScript performance and addition of APIs such as WebRTC, efficient computer vision processing can be realized on web clients. Through novel engineering techniques, we translate a popular open-source computer vision library (OpenCV) from C++ to JavaScript and optimize its performance for the web environment. We demonstrate that hundreds of computer vision functions run in browsers with performance close to their original C++ version.
Field Programmable Gate Arrays (FPGA)s are a promising solution to mitigate the computational cost of vision algorithms through hardware pipelining and parallelism while providing excellent power efficiency. However, an efficient FPGA implementation of vision algorithm requires hardware design expertise and a considerable amount of engineering person-hours. We show how high-level graph-based specifications, such as OpenVX can significantly improve FPGA design productivity. Since such abstractions exclude implementation details, different implementation configurations that satisfy various design constraints, such as performance and power consumption, can be explored systematically. They also enable a variety of local and global optimizations to apply across the algorithms.

 
PhD Defense: Event Detection and Estimation Using Distributed Population Owned Sensors

Name: Ahmed Mokhtar Nagy Ibrahim

Chair: Prof. Ahmed Eltawil

Date: August 7th, 2019

Time: 1:00 pm

Location:  EH 2210 – EECS Chair’s Conference Room

Committee: Ahmed Eltawil(Chair), Ender Ayanoglu, and Lee Swindlehurst

Title:”Event Detection and Estimation Using Distributed Population Owned Sensors ”

Abstract:
Smart phones are an indispensable tool in modern day-to-day life. Their widespread use has spawned numerous applications targeting diverse domains such as bio-medical, environment sensing and infrastructure monitoring. In such applications, the accuracy of the sensors at the core of the system is still questionable, since these devices are not originally designed for high accuracy sensing purposes. In this thesis, we investigate the accuracy limits of one of the commonly used sensors, namely, a smart phone accelerometer. As a use case, we focus on utilizing smart phone accelerometers in structural health monitoring (SHM). Using the already deployed network of distributed citizen-owned sensors is considered a cheap alternative to standalone sensors. These devices can capture floors vibration during disasters, and consequently compute the instantaneous displacement of each floor. Hence, damage indicators defined by government standards such as peak relative displacement can be estimated. In this work, we study the displacement estimation accuracy and propose a zero-velocity update (ZUPT) method for noise cancellation. Theoretical derivation and experimental validation are presented, and we discuss the impact of sensor error on the achieved building classification accuracy. Moreover, in spite of the presence of sensor error, SHM systems can be resilient by adopting machine learning. Several algorithms such as support vector machine (SVM), K-nearest neighbor (KNN) and convolutional neural network (CNN) are adopted and compared. Techniques for addressing noise levels are proposed and the results are compared to regular noise cancellation techniques such as filtering.

Finally, since most previous work focused on modelling the sensor chip error itself, we study other sources of error such as sampling time uncertainty which is introduced by the device operating system (OS). That type of error can be considered a major contributor to the overall error, specially for sufficiently large signals. Hence, we propose a novel smart device accelerometer error model that includes the traditional additive noise as well as sampling time uncertainty errors. The model is validated experimentally using shake table experiments, and maximum likely-hood estimation (MLE) is used to estimate the model parameters. Moreover, we derive the Cramer-Rao lower bound (CRLB) of acceleration estimation based on the proposed model.

 
PhD Defense: Cooperative Power and Resource Management for Heterogeneous Mobile Architectures

Name: Chenying Hsieh

Date: Wednesday Aug 7, 2019

Time: 2:00 pm
Location: Donald Bren Hall 4011
Committee: Nikil Dutt (Chair), Tony Givargis, and Ardalan Amiri Sani
Title: Cooperative Power and Resource Management for Heterogeneous Mobile Architectures
 
Abstract:
Heterogeneous architectures have been ubiquitous in mobile system-on-chips (SoCs). The demand from different application domains such as games, computer vision and machine learning which requires massive parallelism of computation has driven the integration of more accelerators into mobile SoCs to provide satisfactory performance energy-efficiently.These on-chip computing resources typically have their individual runtime systems including: (1) a software governor: continuously monitors hardware utilization and makes decisions of trade-off between performance and power consumption. (2) software stack: allows application developers to program the hardware for general purpose computation and perform memory management and profiling. As computation of mobile applications may demand all sorts of combinations of computing resources, we identify two problems: (1) individual runtime can often lead to poor performance-power trade-off or inefficient utilization of computing resources. (2) existing approaches fail to schedule subprograms among different computing resources and further lose the opportunity to avoid resource contention to gain better performance.
To address these issues, we propose a holistic approach to coordinate different runtime regrading application performance and energy efficiency in this dissertation. We first present MEMCOP, a memory-aware collaborative CPU-GPU governor that considers both the memory access footprint as well as the CPU/GPU frequency to improve energy efficiency of high-end mobile game workloads by performing dynamic voltage and frequency scaling (DVFS). Second, We present a case study executing a mix of popular data-parallel workloads such as convolutional neural networks (CNNs), computer vision filters and graphics rendering kernels on mobile devices, and show that both performance and energy consumption of mobile platforms can be improved by synergistically deploying these underutilized compute resources. Third, we present SURF: a self-aware unified runtime framework for parallel programs on heterogeneous mobile architectures. SURF supports several heterogeneous parallel programming languages (including OpenMP and OpenCL), and enables dynamic task-mapping to heterogeneous resources based on runtime measurement and prediction.The measurement and monitoring loop enables self-aware adaptation of run-time mapping to exploit the best available resource dynamically.
We implemented all the software components on real-world mobile SoCs and evaluate our proposed approaches with mobile games and mix of parallel benchmarks and CNN applications accordingly.

 
PhD Defense: Low-Power Integrated Circuits For Biomedical Applications

Title: “Low-Power Integrated Circuits For Biomedical Applications”

Name: Karimi Bidhendi, Alireza

Chair: Professor Payam Heydari

Date: August 6, 2019

Time: 1 pm

Location: Calit2,  Room 3008

Abstract:

With thousands new cases of spinal cord injury reported everyday, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs, such a state severely deteriorates a patients quality of life and may even lead to additional medical conditions. Therefore, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient’s brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts, having high spatial resolution and signal to noise ratio, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted.

To implement a fully implantable system, low-power and miniaturized electronics are needed to reduce heat generation, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system’s components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system, namely, ultra low-power brain signal acquisition front-ends, a low-power and inductorless MedRadio transceiver, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillators generate the reference signal for other system components such as analog to digital converters. Novel techniques to improve important performance parameters (power consumption, low noise operation and interference resilience) have been introduced. Electrical, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design.

 
Data-Driven Modeling of Cyber-Physical Systems using Side-Channel Analysis

Title: “Data-Driven Modeling of Cyber-Physical Systems using Side-Channel Analysis”

Name: Sujit Rokka Chhetri

Date: May 20, 2019

Time: 3:00 PM

Location: EH 5200

Committee: Prof. Mohammad Al Faruque (Chair), Prof. Pramod Khargonekar, Prof. Fadi Kurdahi

Abstract:

Cyber-Physical System consists of the integration of computational components in the cyber-domain with the physical-domain processes. In cyber-domain, embedded computers and networks monitor and control the physical processes, and in the physical-domain the sensors and actuators aid in interacting with the physical world. This interaction between the cyber and physical domain brings unique modeling challenges one of which includes the integration of discrete models in cyber-domain with the continuous physical domain processes. However, the same cyber-physical interaction also opens new opportunities for modeling. For example, the information flow in the cyber-domain manifests physically in the form of energy flows in the physical domain. Some of these energy flows unintentionally provide information about the cyber-domain through the side-channels.

In this thesis, the extensive analysis of the side-channels (such as acoustic, magnetic, thermal, power and vibration) of the cyber-physical system is performed. Based on this analysis data-driven models are estimated. These models are then used to perform security vulnerability analysis (for confidentiality and integrity), whereby, new attack models are explored.  Furthermore, the data-driven models are also utilized to create a defensive mechanism to minimize the information leakage from the system and to detect attacks to the integrity of the system. The cyber-physical manufacturing systems are taken as use cases to demonstrate the applicability of the modeling approaches.

Finally, the side-channel analysis is also performed to aid in modeling digital twins of the cyber-physical systems. Specifically, a novel methodology to utilize low-end sensors to analyze the side-channels and build the digital twins is proposed. These digital twins are used to capture the interaction between the cyber-domain and the physical domain of the manufacturing systems, and aid in process quality inference and fault localization. Using side-channels these digital twins are kept up-to-date, which is one of the fundamental requirements for building digital twins.

 
Cyber-Physical Systems Approach to Irrigation Systems

Title: “Cyber-Physical Systems Approach to Irrigation Systems”

Name: Davit Hovhannisyan

Date: March 5, 2019

Time: 4:00PM

Location: EH 3206  (CECS conference room)

Committee:  Prof. Fadi Kurdahi (Chair), Prof. Ahmed Eltawil, Prof. Mohammad Al Faruque

Abstract:

Semiconductor industry has successfully brought silicon technology to price point that it is accessible for application domains such as irrigation systems, which wastefully utilizes 70% of all fresh water. Moreover, worldwide fresh water resources will soon reach a deficit due to ever growing demand, while the state of the art precision irrigation systems utilize sophisticated water delivery drip lines, yet are only controlled at source by the gut of the end user. This work demonstrates that scientific foundation of cyber-physical systems can be used to design automated, distributed and intelligent precision irrigation systems that improve irrigation efficiency. Thus, this work explores and analyzes in depth the cross section of irrigation practices and cyber-physical systems knowledge to show a path toward a successful adaptation of silicon technology that solves one of the greatest challenges of the 21st century, the fresh water scarcity. To that end, this work presents contributions that complete a novel vision for next generation precision irrigation systems, which can be grouped into three main thrusts: (1) circuit inspired models for irrigation system components and scheduling strategies by analogy method, (2) CPS approach based (a) design methodology capable of comparing irrigation controllers, (b) simulation tools and software for analyzing the distributed behavior of the specialized irrigation controllers, (c) topology adaptation technique that utilizes multi-graphs to mine the hydro-wireless topology of the IoT controllers, and (d) a distributed controller implementation with novel energy harvesting and low power support for irrigation controllers and sensors, (3) overhead vision solutions for health and growth monitoring. The observations, analysis and insight from experimental studies were in collaboration with Rancho California Water District, growers and practitioners.

 
Control System Design Automation Using Reinforcement Learning

Title: “Control System Design Automation Using Reinforcement Learning”

Name: Hamid Mirzaei

Date: Tuesday, November 20, 2018

Time: 1:00 p.m.

Location: Donald Bren Hall 3011

Committee: Professor Tony Givargis (Chair), Professor Eli Bozorgzadeh, Professor Ian Harris

Abstract:

Conventional control theory has been used in many application domains with great success in the past decades. However, novel solutions are required to cope with the challenges arising from complex interaction of fast growing cyber and physical systems. Specifically, integration of classical control methods with Cyber-Physical System (CPS) design tools is a non-trivial task since those methods have been developed to be used by human expert and are not intended to be part of an automatic design tool.

On the other hand, the control problems in emerging Cyber-Physical Systems, such as intelligent transportation and autonomous driving, cannot be addressed by conventional control methods due to the high level of uncertainty, complex dynamic model requirements and operational and safety constraints.
In this dissertation, a holistic CPS design approach is proposed in which the control algorithm is incorporated as a building block in the design tool. The proposed approach facilitates the inclusion of physical variability into the design process and reduces the parameter space to be explored. This has been done by adding constraints imposed by the control algorithm.
Furthermore, Reinforcement Learning (RL) as a replacement for convection control solutions are studied in the emerging domain of intelligent transportation systems. Specifically, dynamic tolling assignments and autonomous intersection management are tackled by the state-of-the-art RL methods, namely, Trust Region Policy Optimization and Finite-Difference Gradient Descent. Additionally, Q-learning is used to improve the performance of an embedded controller using a novel formulation in which cyber-system actions, such as changing control sampling time, is combined with the physical action set of the RL agent. Using the proposed approach, it is shown that the power consumption and computational overhead of the embedded control can be improved.
Finally, to address the current lack of available physical benchmarks, an open physical environment benchmarking framework is introduced. In the proposed framework, various components of a physical environment are captured in a unified repository to enable researchers to define and share standard benchmarks that can be used to evaluate different reinforcement algorithms. They can also share the realized environments via the cloud to enable other groups perform experiments on the actual physical environments instead of currently available simulation-based environments.