Seminars at CECS

When Lyapunov meets Church, automated synthesis of complex systems emerges

Title: When Lyapunov meets Church, automated synthesis of complex systems emerges

Speaker: Prof. Majid Zamani, Technische Universität München, Germany

Date: Thursday, September 24, 2015

Time: 3:30 p.m.

Location: Engineering Colloquia Room 2430

Host: Faryar Jabbari and Solmaz S. Kia

Abstract: Software plays a crucial role in many everyday applications. Modern vehicles and
airplanes, for instance, use interacting software and hardware components to control steering, fuel in
jection, and airbag deployment. These applications are examples of cyber-­‐physical systems (CPS), where software components interact tightly with physical systems. Recent advances in device manufacturing, computation, storage, and networking have made tremendous advances in hardware and systems platforms for CPS. However, the development of core software controllers that run on these systems is still ad hoc and error-­‐prone. Many CPS applications are safety-­‐critical, and much of the engineering costs today are consumed with ensuring that software works correctly. In this talk, I will proposes a transformative design process, in which the controller code is automatically synthesized from higher-­‐level correctness requirements. Requirements for modern CPS applications go beyond conventional requirements in control theory (stability, synchronization, and tracking) and
beyond traditional protocol design in computer science. Accordingly, I will propose unified methodologies for automatic controller synthesis by combining techniques from discrete systems theory from computer science with continuous dynamical systems from control theory. The proposed automated synthesis of correct-­‐by-­‐ construction controllers holds the potential to develop complex yet reliable CPS applications while considerably reducing verification and validation costs.
Bio: Majid Zamani is an assistant professor in the Department of Electrical and

Computer Engineering at Technische Universität München where he leads the Hybrid Control Systems Group. He received a Ph.D. degree in Electrical Engineering and an MA degree in Mathematics both from University of California, Los Angeles in 2012, an M.Sc. degree in Electrical Engineering from Sharif University of Technology in 2007, and a B.Sc. degree in Electrical Engineering from Isfahan University of Technology in 2005. From September 2012 to December 2013, he was a postdoctoral researcher in the Delft Centre for Systems and Control at Delft University of Technology. Between December 2013 and May 2014, he was an assistant professor at Delft University of Technology.nd RSS). He is the Editor-­‐in-­‐Chief of the Springer journal Autonomous Robots.

 
Mitigating BTI-induced Device Degradation: A Circuit and System Persepctive

Title: Mitigating BTI-induced Device Degradation: A Circuit and System Persepctive

Speaker: Professor Ing-Chao Lin, National Cheng Kung University, Taiwan

Date and Time: Monday, February 8, 2016 at 1:30 P.M.

Location: Donald Bren Hall 3011

Host: Professor Nikil Dutt

Abstract: Bias temperature instability which causes a shift in the transistor’s threshold voltage and decreases circuit switching speed has become a major reliability concern. In this talk, I will introduce the techniques to mitigate device degradation at the circuit and system level, and provide design guidelines to deal with device degradation. The future trend on device degradation will be introduced as well.

Biography: Prof. Ing‐Chao Lin received his M.S. degree from Dept. of Computer Science and Information Engineering, National Taiwan University and Ph.D. degree from Dept. of Computer Science and Engineering, the Pennsylvania State University 2001 and 2007, respectively. From 2007 to 2009, he is a staff R&D engineer in Real Intent Inc., CA, USA, where he is working on Real Intent’s automatic timing exception verifier. His research interest includes reliable power‐aware system, electronic design automation, and computer architecture. He has authored or co‐authored more than 50 scientific papers and is a committee member of many technical conferences. He is a senior member of IEEE and he is thechair of IEEE Tainan Young Professional group. He is the recipient of 2015 Excellent Young Researcher Award by Chinese Institute of Electrical Engineering. He is currently a visiting scholar in Dept. of Electrical and Computer Engineering, University of California, Santa Barbara.

 

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Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes

Title: “Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes”

Speaker: Professor Khaled N. Salama, King Abdullah, University of Science and Technology, Saudi Arabia

Date and Time: Thursday, February 18, 2016 at 11:00 A.M.

Location: Engineering Hall 2430

Hosts: Fadi J. Kurdahi and Ahmed Eltawil

Abstract: Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement, or even better, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus, they are attractive from an energy efficiency perspective. In addition, they can be employed in a wide range of sensing applications, such as pressure, humidity, biological, and chemical sensing. However, the capacitive sensor readout circuit—i.e., the capacitance-to-digital converter (CDC) —can be the dominant source of energy consumption in the system. Thus, the development of energy-efficient CDC architectures is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this talk, we propose several energy -efficient CDC architectures for low-energy sensor nodes. In the second part, we study the matching properties of small integrated capacitors, which are an integral component of energy-efficient CDCs. Despite conventional wisdom, we experimentally illustrate that the mismatch of small capacitors can be directly measured, and we report experimental mismatch measurements for sub-femtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors, and we identify the conditions that make one implementation preferable.

Bio: Dr. Salama received his bachelor’s degree with honors from the Electronics and Communications Department at Cairo University in Egypt in 1997, and his master’s and doctorate degrees from the Electrical Engineering Department at Stanford University in the United States, in 2000 and 2005 respectively. He was an assistant professor at RPI between 2005 and 2008. He joined King Abdullah University of science and technology (KAUST) in January 2009 and was the electrical engineering founding program chair till August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA), awarded the Stanford-Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc in 2008. He is the cofounder of ultrawave labs, a biomedical imaging company that was recently acquired. He is the co-author of 90 papers and 10 patents on low-power mixed-signal circuits for intelligent fully integrated sensors and non linear electronics specially memristor devices. He is a senior member of IEEE.

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Distinguished Lecture Series

Title: “Towards Computer-Aided Design of Electrical Energy Systems: Challenges and Solutions”

Speaker: Professor Massimo Poncino, Polytechnic University of Turin, Italy

Date and Time: Friday, April 22, 2016 at 11:00 A.M. – 12:00 P.M.

Location: Engineering Hall 2430

Hosts: Professor Mohammad Al Faruque

Abstract: Electrical energy systems (EESs) include energy generation, distribution, storage, and consumption, and involve many diverse components and sub-systems to implement these tasks. In this talk we discuss fundamental concepts towards a first attempt in applying EDA design methodologies that are widely used for electronics systems design to the case of the design of EESs. CAD for EESs encompasses modeling, simulation, design and optimization and is a challenging task that mandates a multidisciplinary and heterogeneous approach. We identify similarities and differences between electrical energy systems and electronics systems in order to inherit as much as possible the profound legacy resources of EDA. The talk analyzes in deeper details the issue of representation, modeling, and simulation of EESs, tasks that naturally precede synthesis and optimization in a typical design flow.
Bio: Massimo Poncino is Full Professor of Computing Systems at Politecnico di Torino. Prior to that,
he was an Associate Professor (from 2004 to 2006) at Politecnico di Torino, Associate Professor (from 2001 to 2004) at Università di Verona, and Assistant Professor (from 1995 to 2001) at Politecnico di Torino. From 1993 to 1994 he was a Visiting Scientist at the Department of Electrical and Computer Engineering of the University of Colorado, Boulder, USA. He holds a Dr. Eng. degree in Electrical Engineering (1989) and a PhD degree in Computer Engineering, both from Politecnico di Torino (1993).His research interests include the design automation of digital systems, with emphasis on low
-power embedded systems, modeling and the simulation of systems -on- chip, and automatic synthesis of digital systems. He has coauthored more than 300 publications in the above areas, including one book on energy -efficient memory design. Massimo Poncino has served as member of Technical Program Committee of more than 50 IEEE and ACM conferences. He was the Technical Program Chair of the 2011 IEEE/ACM Symposium on Low-Power Electronics and Design and General co-Chair for the same conference in 2012. He has served in the Editorial Board of the IEEE Transactions on CAD from 2006 to 2011, and is currently serving in the Editorial Board of IEEE Design & Test and ACM Transactions on Design Automation of Electronic Systems (TODAES). Prof. Poncino is a Senior Member of IEEE, member of the ACM SIGDA Low -Power Technical Committee, and a Member the Circuit and Systems Society.

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Circuits and Systems Seminar Series

Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”

Speaker: Prof Mingoo Seok, Columbia University, New York, NY

Date and Time: Friday, April 22, 2016 at 3:00 P.M. – 4:00 P.M.

Location: Engineering Hall 2430

Hosts: Professor Payam Heydari

Abstract: In this talk, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage, chip temperature, manufacturing process, and transistor aging have imposed a large amount of pessimistic margins in clock frequency, voltage, and device size, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead, in-sit, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing, (3) self-testing circuits and frameworks for in-field & in-sit aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented.

Bio: Mingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University, South Korea, in 2005, and the MS and PhD degree from University of Michigan in 2007 and 2011, respectively, all in electrical engineering. He was a member of technical staff in Texas Instruments, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems, including ultra-low-power computing systems, computing systems for machine learning, adaptive circuits and architecture, and non-conventional computing systems. He received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies, 2005 Doctoral Fellowship from the same organization, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013, and IEEE Transactions on VLSI Systems since 2015.

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CECS Hosts IWCR 2016
 
Area/speed tradeoffs in a retargetable FPGA-optimized processor core

Speaker:  Marco Zec, University of Zagreb

Title:  “Area/speed tradeoffs in a retargetable FPGA-optimized processor core”

Date:  Friday, July 15, 2016

Time:  11:00 AM

Location:  CECS Conference Room (Engineering Hall 3206)

Host:  Prof. Daniel Gajski

Abstract: Can portable yet efficient, FPGA-optimized processor cores be constructed using generic HDL, without depending on any vendor-specific primitives?  In this talk we will discuss the techniques applied for achieving a balance between instruction throughput and FPGA resource utilization in a synthesizable scalar core which outperforms its proprietary counterparts (MicroBlaze, Nios, Cortex-M3) by 20% to 40% in industry-standard integer benchmarks (CoreMark, Dhrystone per MHz) while
occupying less than 1000 6-input LUTs, and less than 650 LUTs in an area-optimized configuration.  The core can be retargeted to execute subsets of either the emerging RISC-V or the traditional MIPS instruction sets, and is supported by contemporary GNU-based software toolchains.

Bio: Marko Zec received a BSc in electrical engineering from the University of Zagreb, where since 2005. he has been working as a project scientist on various computer networks projects with funding from ICSI Berkeley, the FreeBSD foundation, Boeing Integrated Defense Systems, and Ericsson. His research interests include operating systems, computer networks, software-based packet processing datapaths, and programmable logic.

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Mobile Technology Enabling Frictionless HealthCare

Title: “Mobile Technology Enabling Frictionless HealthCare”

Speaker: Aiman Abdel-Malek, Vice President, Engineering, Qualcomm Life, Founder & CEO, Frictionless Life Analytics

Date:  Tuesday, November 10, 2015

Time:  3:00 p.m.

Location:  Engineering Hall 2430

Host: Prof. Fadi J. Kurdahi

Abstract: With Smart mobile devices being the fastest growing consumer platform in history, it is becoming a huge enabler to new business models that reduce friction in daily life. Aiman will introduce how mobile technology is creating solutions to many of the current healthcare issues and enabling moving care from the hospital to the home.

Bio: Aiman joined Qualcomm Life from General Electric’s Healthcare Division in Sept 2012, where he served as GM and CTO for the Global Services Technology business, a $5 billion division of GE healthcare. There he led a global engineering team responsible for the development of software and systems platforms for predictive remote service technology and healthcare operational efficiency and quality applications. Aiman served GE for 25 years; 10 years in R&D helping the development of GE’s first digital x-ray mammography system and digital Ultrasound system. He then moved to GE Transportation to start and manage the first Satellite wireless-based Locomotive Remote Predictive Services business, which currently runs on over 20,000 locomotives. Afterward, he took an expat assignment in the United Kingdom, as technology managing director for the Pipeline Inspection Services, a $400 million global business unit of GE Oil and Gas. Aiman’s technical expertise is in the development of vision inspired signal processing algorithms for aerospace, industrial and medical applications. He earned his PhD in Systems & Biomedical engineering from the University of Southern California, completing post-doctoral research at UCLA in neurology. He is a senior member of the IEEE and holds over 22 US and international patents. He serves as a member of the Scientific Advisory Board for the Qualcomm-Xprize Tricorder competition. Also, he served on GE’s Corporate Software Board, and as an executive leader for the Image & Signal Processing Technology Council for GE Healthcare. Aiman recently founded his own company, which aims at helping guide California startups & ventures move from “concept” to “scale” in most frictionless path. He is also a Board Advisor to few startups.

 

 
Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems

Speaker:  Prof. Muhammad Mustafa Hussain, King Abdullah University of Science and Technology (KAUST)

Title:  “Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems”

Date:  Tuesday, April 21, 2015

Time:  2:00 PM

Location:  Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host:  Prof. Fadi Kurdahi

Abstract: Our research is focused on heterogeneous electronic materials and high-performance complementary metal oxide semiconductor (CMOS) based tunable shape-size-conformity wearable interactive electronics and systems for smart living (computation-communication-infotainment) through internet of everything and a sustainable future (healthcare-water-food-environment-security). For scientific exploration, we make collective use of the materials, processes and device architecture leveraging multidisciplinary tracks of material science, bioengineering, mechanical, environmental engineering and computer science. As engineering tool, we use CMOS technology extensively due to its industrial relevance, maturity and reliability for rapid tech transfer.
To bridge between the high-performance state-of-the-art electronics and emerging soft-materials based flexible-stretchable electronics. we have developed various generic batch processes using CMOS technologies to transform any already processed Integrated Circuitry (IC) or arrays of devices to be fabricated on virgin substrates (thin film based, examples include but not limited to: silicon, silicon germanium, indium phosphide, gallium arsenide, etc.) into flexible and stretchable one [ACS Nano 2014, pss-RRL 2014]. These processes are cost effective ($1.25/cm2), non-abrasive and retain high-performance, energy-efficiency, ultra-large-scale-integration density as obtained in today’s state-of-the-art electronics. Often the transformed fabrics (ultra-thin version of the bulk thin film substrates with pre-fabricated devices) are semi-transparent due to the presence of the process originated vertical channels. As per ITRS 2014 metrics, the processes are fully scalable down to 2 nm technology node. Using these techniques we have demonstrated high-κ/metal gate based planar and non-planar nano-scale (sub-20 nm) CMOS logic devices [Adv. Mater. 2014 (cover page), ACS Nano 2014, APL 2013, pss-RRL 2013 (cover pages), IEEE TED 2013, pss-RRL 2013, Sci. Rep. 2013, pss-RRL 2013], memory [Adv. Electronic Mater. 2015, Microelect. Engr. 2014], micro-scale thermoelectric generators [Small 2013 (frontispiece)], micro lithium ion batteries (150 μAh/cm2 normalized capacity), MEMS devices [MEMS 2014], smart thermal patch using copper stretched up to 800% [Adv. Healthcare Mater. 2015 (frontispiece)], mono-crystalline silicon stretched up to 1000% [APL 2014]. Variety of device demonstrations on wide range of inorganic thin films using this technique proves the efficiency and versatility of it. Our research greatly complements the $150M Flexible Hybrid Electronics Manufacturing Initiative (FHEMII) – recently introduced by the US Department of Defense: “Highly tailorable devices on flexible, stretchable substrates that combined thinned CMOS components with components that are added via printing process”.

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Reviving Processing-in-Memory for Large Data Workload on Existing Computer Architecture

Speaker:  Professor Sungjoo Yoo, Computing and Memory Architecture Lab, Seoul National University

Title:  Reviving Processing-in-Memory for LArge Data Workload on Existing Computer Architecture

Date:  Tuesday, July 14, 2015

Time:  11:00 AM

Location:  Donald Bren Hall 3011

Host:  Nikil Dutt

Abstract: Processing-in-memory (PIM) is rebounding from its unsuccessful attempts in 1990s due to two main reasons, recent advances in 3D stacking technologies and emerging large data workload.  In this talk, we present two of our recent works, PIM for large data workload and combining PIM with the existing computer architecture.
Graph data are becoming more and more popular in many areas such as machine learning, social network analysis, etc.  Graph computation is to process a query to the graph database, e.g., finding the most popular personality.  Graph computation is characterized by computation parallelism (per-vertex parallel computation) and significant random memory accesses (to neighbor vertices).  The conventional architecture is not well suited for this type of workload.  We present a programmable PIM accelerator for large-scale graph processing called Tesseract.  Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design.  It also includes two hardware prefecthers specialized for memory access patterns of graph processing, which operate base on the hints provided by our programming model.
In order to make best use of PIM in more areas, it is required to integrate the PIM architectures with existing systems in a seamless manner.  The current PIM proposals lack due to two common characteristics: unconventional programming models for in-memory computation units (as programmable co-processors) and lack of ability to utilize large on-chip caches.  We propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data.  The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions, which we call PIM-enabled instructions, to invoke in-memory computation.  This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification.

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Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing

Speaker:  Prof. Jörg Conradt

Title:  Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing

Date:  Tuesday, June 2, 2015

Time:  3:00 p.m.

Location:  Donald Bren Hall 4011

Host:  Jeff Krichmar and Nikil Dutt

Abstract:

In recent decades the field of Computer Vision has developed sophisticated algorithms for problems such as object tracking or motion extraction based on sequences of high-resolution camera images. Applying such algorithms in real-time robotics reveals an inherent problem: they typically require high data bandwidth and high processing power, which results in substantial computing machinery and/or delayed processing of data. As part of an optimized biological solution for vision, our brain developed retinal receptor cells that largely respond with asynchronous events (“neural spikes”) to temporal changes of brightness. Such encoding of visual information substantially reduces the amount of transmitted data and simultaneously increases temporal precision.

Recently “silicon retinas” have been developed as specialized vision sensors to provide such neuro-inspired vision input for technical systems. Visual information obtained from these sensors differs substantially from traditional sequences of images, which requires an “event-based” redesign of computer vision algorithms. This talk introduces the neuro-inspired vision sensors and presents event-based algorithms for applications such as real-time computation of optic flow and visual object tracking at high update rates on minimalistic computing hardware.

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Design Technologies for Embedded Multiprocessor Systems-on-Chip

Speaker:  Prof. Rainer Leupers

Title: Design Technologies for Embedded Multiprocessor Systems-on-Chip

Date: Thursday, April 9, 2015

Time: 11:00am

Location: Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host: Mohammad Al Faruque

Abstract:

The trend towards Multicore and even Manycore architectures affects virtually all areas of computing today. Especially in the mobiles and consumer domains, an extremely high architectural efficiency (MIPS/Watt) is required. In order to manage the complexity of multi-billion transistor IC designs with dozens of heterogeneous processing engines, advanced Electronic System Level (ESL) tools are required. ESL can be roughly subdivided into four categories: architecture modeling and optimization, application SW mapping, simulation and verification, and efficient IP block design. After a general introduction to embedded MPSoC (Multiprocessor Systems-on-Chip) architectures and ESL technologies, this seminar talk will cover selected aspects from the above four domains, in particular ESL power estimation, embedded multicore SW development, fast virtual platforms, and application-specific processor design.

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Architectural Support for Security in Emerging Platforms

Speaker: Nael Abu-Ghazaleh

Title: Architectural Support for Security in Emerging Platforms

Date: Wednesday, March 4, 2015

Time: 10:00am

Location: Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host: Fadi Kurdahi

Abstract:

Computer systems are facing a growing threat from increasingly motivated, organized and sophisticated attackers.  The problem is complicated by the rapid evolution that computing platforms are experiencing towards mobile and embedded devices, as well as many-core systems, distributed systems, virtualization and clouds.  These emerging platforms offer new system and use models and therefore are subject to new vulnerabilities and threat models.  This talk motivates the role that computer architecture must play in securing current and emerging systems.  I will define this role spanning three primary directions: (1) new security models for protecting not only systems but also applications; (2) architecture support for monitoring to improve resilience to attacks, but also to rapidly detect and contain successful attacks; and (3) Security for emerging architectures.  I will animate each of these directions with examples from our recent work.

 
Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks

Speaker: Francesco Regazzoni

Title: Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks

Date: Tuesday, March 3, 2015

Time: 2:00pm

Location: Donald Bren Hall 3011

Host: Nikil Dutt & Rosario Cammarota

Abstract:

Physical attacks exploit the physical weaknesses of cryptographic devices to reveal the secret information stored on them. Countermeasures against these attacks are often considered only in the later stages of the full design flow, and applied manually by designers with strong security expertise. This approach, however, negatively affects the robustness, the cost, and the production time of secure devices.

In view of this increasingly relevant problem, it is crucial to address the design challenges associated with the proliferation of physical attacks, developing a methodology to automate the design and the verification of secure embedded systems.

This talk focuses on one type of physical attacks, the differential power analysis (DPA), and presents the design and the implementation of the infrastructure needed to enable the automatic application and verification of DPA countermeasures.

 
Connected Context Computing for Smart IoT

Speaker: Jane Yung-jen Hsu

Title: Connected Context Computing for Smart IoT

Date: Tuesday, February 10, 2015

Time: 3:30pm

Location: Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host: Professor Kwei-Jay Lin

Abstract:

We are witnessing the explosion of connected devices, or the so-called Internet of Things, in our everyday lives. This new trend has created new opportunities to monitor human activities and to configure environments for comfort, security, or energy savings. In the US, buildings account for roughly 40% of total energy usage, with major contributions from the cooling demands. While most people have no intention of wasting energy, they are often unaware of the energy footprint of their daily routines. Activity recognition is a key capability for a smart environment to offer timely services and intelligent interactions with people.

In this talk, I will introduce connected context computing and its significance in enabling our vision of smart IoT. In particular, I will share our experience on monitoring the Computer Science building on NTU campus to improve its air conditioning and space utilization. First, an agent-based HVAC service is designed to analyze cooling demands and wastes. Second, experiments on SweetFeedback are conducted to encourage energy-saving behaviors. Third, crowd sourcing cyber-physical agents are deployed to acquire status labels for activity recognition from people situated in the environment. Â Our experiments showed that context computing, predictive analytics, and proactive control are the fundamental building blocks for a smart IoT framework that can SCALE (Sense, Communicate, Analyze, Learn, Expect and Effect).