Seminars at CECS

“ZeNA: Zero-Aware Neural Network Accelerator”

Title: “ZeNA: Zero-Aware Neural Network Accelerator”

Speaker: Professor Sungjoo Yoo, Seoul National University, South Korea

Date and Time: Wednesday, December 6, 2017 at 4:00PM-5:00PM

Location: DBH 4011

Abstract:
Accelerating convolutional neural networks (CNNs) is becoming more and more important due to their ever-in-creasing range of applications, e.g., image and video classification in data centers. Based on the observations that the significant amount of weights and activations in CNNs can be zero without losing quality, we propose a novel zero-aware hardware accelerator for CNNs named ZeNA, which exploits both zero weights and activations. Moreover, we report zero-induced load imbalance problems at two levels of scale in a zero-aware parallel CNN accelerator and present zero-aware kernel allocation and dynamic work group allocation as solutions. According to our experiments with a cycle-accurate simulation model, RTL, and layout design, ZeNA achieves 4.4×/2× (AlexNet) and 5.6×/2.4× (VGG-16) speedup compared to an existing state-of-the-art zero-agnostic/zero-activation-aware accelerator.

Biography:
Sungjoo Yoo received Ph.D. from Seoul National University in 2000. From 2000 to 2004, he was a researcher at SLS group, TIMA laboratory, Grenoble France.
From 2004 to 2008, he was a senior/principal engineer at System LSI, Samsung Electronics. From 2008 to 2015, he was an assistant/associate professor at POSTECH.
In 2015, he joined Seoul National University. His current research interests include algorithm/software/hardware optimizations for deep neural networks including reinforcement learning for runtime optimization, network compression, quantization, and hardware accelerators.

 

 
“Network Resource Management in Cyber-Physical Systems”

Title: “Network Resource Management in Cyber-Physical Systems”

Speaker: Dr. Xiabo Sharon Hu, University of Notre Dame, USA

Date and Time: Friday, November 17, 2017 at 2:00PM-3:00PM

Location: ICS 432

Abstract:

A cyber-physical system (CPS) is a system built from close integration of computational fabrics and physical components. Examples of such systems include avionic systems, industrial control and civil infrastructure monitoring. In a CPS, sensors and actuators are used to monitor and control the physical components while the computational fabrics determine the control values for the actuators based on the sensed data. All CPSs require timely delivery of sensed data from sensors to the computing fabrics and control signals from the computing fabrics to actuators. Managing the limited resources (e.g., computation power and communication bandwidth) to meet the timing requirements in a CPS is a challenging task. Even more challenging is that CPSs should degrade gracefully in the presence of various external disturbances such as failure in critical civil infrastructures and malicious attacks.

In this talk, I first give a general introduction of WNCSs and the challenges that they present to network resource management. In particular, I will discuss the complications due to external disturbances and the need for dynamic data-link layer scheduling. I then highlight our recent work that aims at tackling this challenge. Our work balances the scheduling effort between a gateway (or access points) and the rest of the nodes in a network. It paves the way towards decentralized network resource management in
order to achieve scalability. Experimental implementation on a wireless test bed further validates the applicability of our proposed research. I will end the talk outlining our on-going effort in this exciting and growing area of research.

Xiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, Notre Dame, Indiana, USA. Her research interests include low-power system design, real-time embedded systems, circuit and architecture design with emerging technologies, and hardware/software co-design. She has published more than 300 papers in these areas, and received the Best Paper Award from the Design Automation Conference in 2001 and from the IEEE Symposium
on Nanoscale Architectures in 2009. She is the General Chair of Design Automation Conference in 2018. She is an Associate Editor for ACM Transactions on Cyber- Physical Systems, and also served as Associate Editor for IEEE Transactions on VLSI, etc. Sharon Hu is a Fellow of the IEEE.

Biography:

Xiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, Notre Dame, Indiana, USA. She also holds a joint appointment in the department of Electrical Engineering at the same university. She received B.S. degree from Tianjin University, China, M.S. degree from Polytechnic University of New York, and Ph.D. degree from Purdue University. She worked for General Motors Research Labs for almost 4 years before she started her academic career. Between 1993 and 1996, she was an assitant professor in the department of Electrical and Computer Engineering at Western Michigan University, Kalamazoo, Michigan, USA.

Her research interests include analysis and design of low power, real-time, and embedded systems, computing with emerging technologies, and computational medicine. She has published more than 200 referred papers in these areas and received numerous research grants from both the U.S. government agencies and private industry. She received the CAREER award from U.S. National Science Foundation in 1997. She received the Best Paper Award from the ACM/IEEE Design Automation Conference in 2001 and from the IEEE Symposium on Nanoscale Architectures in 2009. Another paper of hers was named one of “The Most Influential Papers of 10 Years Design, Automation, and Test in Europe Conference (DATE)”.

Sharon is currently Associate Editor for ACM Transactions on Embedded Computing and Co-Chair of the Technical Program Committee of 2014 Design Automation Conference (DAC). She also served as Associate Editor for IEEE Transactions on VLSI and ACM Transactions on Design Automation of Electronic Systems. She has served as guest editors for several different journals/magazines such as the IEEE Computer Magazine and IEEE Transactions on Industrial Informatics. She was the Technical Program Co-Chair of the 9th International Symposium on Hardware/Software Codesign (CODES’2001) and the General Co-Chair of the same conference in 2002. She also served or is serving on the program committee of a number of conferences such as Design Automation Conference (DAC), International Conference on Computer-Aided Design (ICCAD), Design, Automation and Test in Europe Conference )DATE), IEEE Real-Time Systems Symposium (RTSS), and IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), etc.

At the University of Notre Dame, Sharon had been the Director of Graduate Studies for 10 years in the department of Computer Science and Engineering, and was Senior Assistant Provost for ND International between 2012–2013. Currently, she is the Associate Dean for Professional Development at the Graduate School.

 

 
“ThirdEye: Visual Assist for Grocery Shopping”

Title: “ThirdEye: Visual Assist for Grocery Shopping”

Speaker: Prof. Vijaykrishnan Narayanan, Pennsylvania State University, USA

Date and Time: Wednesday, November 15, 2017 at 11:00AM-12:00PM

Location: 2430 Engineering Hall

Abstract:

Shopping is widely considered as a relaxing leisure activity. However, grocery shopping can be a frustrating experience for those with visual impairment. While getting to a grocery shop itself is not as much of a challenge for them, locating and picking the items in the grocery shelf becomes a task as challenging as picking a needle from the haystack. Imagine picking up five items for your dinner recipe from a typical grocery store in the US that carries around 35,000 unique items and can have more than 30 aisles spanning 45,000 square meters. This talk will showcase synergistic advances in algorithms, architectures and interface design for assisting those with visual impairment to do shopping. We will specifically focus on new non-boolean hardware approaches to significantly impact the energy-efficiency of the overall system.

Biography:

Vijay Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is the director of the NSF Expeditions-in-Computing Program on Visual Cortex on Silicon and a thrust leader for the DARPA-MARCO LEAST Center. He has published more than 400 papers and won several awards in recognition of his research in power-aware systems, embedded systems and computer architecture. He is a fellow of IEEE and ACM.

 

 
“Detecting Hardware Trojans Hidden in Unspecified Design Functionality”

Title: “Detecting Hardware Trojans Hidden in Unspecified Design Functionality”

Speaker: Dr. Nicole Fern, University of California, Santa Barbara

Date and Time: Thursday, November 16th, 2017 at 2:00PM-3:00PM

Location: Donald Bren Hall 3011

Abstract:

Traditional verification methods and metrics attempt to answer the question: does my design correctly perform the intended functionality?  This talk will look at hardware verification from a security perspective, which demands the verification effort answer an additional question: does my design perform malicious functionality in addition to the intended functionality?  The talk will motivate through examples why Hardware Trojans modifying only unspecified design functionality are both powerful and stealthy.  RTL don’t cares and idle cycles in on-chip bus protocols are two examples of unspecified functionality vulnerable to malicious modification that this talk will explore in depth.  This talk will also detail how to formulate the Trojan detection problem as a satisfiability problem in order to leverage existing formal verification tools to highlight Trojans hidden in unspecified functionality.

Biography: 

Nicole Fern received her undergraduate degree in Electrical Engineering from The Cooper Union for the Advancement of Science and Art and her PhD degree in the ECE department at UC Santa Barbara under the advisement of Professor Tim Cheng.  She is now a post-doc at UC Santa Barbara.  Her thesis work focused on developing techniques to verify the absence of Hardware Trojans in unspecified design functionality.  Her current research interests include investigating security issues in emerging memory technologies and at the hardware/software boundary.

 

 

 
“Application Mapping Methodologies for NoC-Based MPSOCs”

Title: “Application Mapping Methodologies for NoC-Based MPSOCs”

Speaker: Jürgen Teich, Friedrich-Alexander Universität Erlangen-Nürnberg (FAU)

Date and Time: Tuesday, November 14, 2017 at 3:00PM-4:00PM

Location: DBH 4011

Abstract: 

In this talk, we give an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures
(MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs
with data dependencies. Here, the nodes represent actors or tasks which are typically activated periodically based on the
availability of data. One prominent domain of applications fitting this model is stream processing. Here, it is often important to guarantee
either bandwidth or execution time requirements. But more recently, also security, energy and reliability aspects impose
constraints on the mapping of the tasks as well as their communication to cores, respectively routes in the underlying NoC.

Concerning mapping methodologies, we first present a class of algorithms that perform “Self-Embedding”. The idea is here that
a source node issues a request to find appropriate resources to embed its sucessor tasks, and so on.
The next class of techniques introduced is called “Hybrid Application Mapping (HAM)”. Here, a careful analysis and
characterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time)
phase called “Design Space Exploration (DSE)”. At run-time, the operating system then only needs to search within such
pre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction.
We present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that
deadlines or throughput requirements will be automatically met for streaming applications.
Finally, we conclude with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC.

Biography:

Jürgen Teich is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany, where he is directing
the Chair for Hardware/Software Co-Design since 2003. He received the M.S. degree (Dipl.-Ing.; with honors)
from the University of Kaiserslautern, Germany in 1989 and the Ph.D. degree (Dr.-Ing.; summa cum laude)
from the University of Saarland, Saarbruecken, Germany, in 1993. In 1994, he joined the DSP design group of Prof. E. A. Lee
in the Department of Electrical Engineering and Computer Sciences (EECS), University of California at
Berkeley (PostDoc). From 1995 to 1998, he held a position at the Institute of Computer Engineering and
Communications Networks Laboratory (TIK), ETH Zurich, Switzerland with his Habilitation
on the topic of `Synthesis and Optimization of Digital Hardware/Software Systems’ in 1996.
From 1998 to 2002, he was Full Professor in the Electrical Engineering and Information Technology
Department, University of Paderborn, Germany.

His current research focuses on electronic design automation of embedded systems
with emphasis on hardware/software co-design, reconfigurable computing and multi-core systems.
Prof. Teich has organized various ACM/IEEE conferences/symposia as Program Chair
including CODES+ISSS´07, FPL´08, ASAP´10, and DATE´2016.
He serves regularly as a TPC member of many program committees including DAC, ASP-DAC, ICCAD, FPL,
ASAP, FPT, FPGA, RECONFIG, ESTIMEDIA, VLSI Design, GECCO, EMO, RTSS, etc.
He also serves in the editorial board of journals including ACM TODAES, IEEE Design and Test and JES and has
edited two text books on Hardware/Software Co-Design and recently a Handbook on this topic (Springer).

Prof. Teich is involved in many interdisciplinary projects on basic research as well as industrial projects.
From 2003-2009, he was an elected board member (Fachkollegiat) of the Deutsche Forschungsgemeinschaft (DFG)
for the area of Computer Architecture and Embedded Systems. He has been the initiator and
coordinator of the DFG priority programme 1148 on “Reconfigurable Computing”.
Since 2010, he has also been the principal coordinator of the Transregional
Research Center 89 “Invasive Computing” funded by the German Research Foundation (DFG).
In 2011, he was elected member of the Academia Europaea.

 

 
Part I: “Development of Low-End Embedded Processors for Some SoC Applications” Part II: “The Application-Specific Design for Signal Processing Applications”

Title: Part I: “Development of Low-End Embedded Processors for Some SoC Applications”
Part II: “The Application-Specific Design for Signal Processing Applications”

Speaker: Prof. Fitzgerald Sungkyung Park, Pusan National University, Busan, South Korea
Prof. Chester Park, Konkuk University, Seoul, Korea

Date and Time: Monday, August 7, 2017, 2:00 PM – 3:00 PM

Location: Donald Bren Hall 3011

Abstract:

Low-end processor cores can be utilized in various SoC applications including IoT, wireless communication, and machine learning.  In this short talk, we will introduce how we designed some low-end integer cores applied to some applications such as deeply embedded IoT and WLAN MAC Soc, and also introduce the basic design of embedded cores for neural networks.

Part II: The application-specific design for signal processing applications tends to necessitate multi-disciplinary knowledge on system, algorithm, architecture and circuit levels.  In this talk, we will introduce our application-specific design approaches for various signal processing applications.  In addition, we discuss several design challenges involved in system-on-a-chip (SoC) design for neural networks, regarding how to customize the on-chip bus architecture.

Biography:

Prof. Fitzgerald Sungkyung Park took his Ph.D. degree in electronics engineering from Seoul National University, Korea, in 2002. He worked for Samsung Electronics from 2002 to 2004, joined Electronics and Telecommunications Research Institute (ETRI) from 2004 to 2006, and worked for Ericsson, Inc., USA, from 2006 to 2009, where he developed mixed-signal circuits for radio transceivers. In 2009, he joined the faculty of Pusan National University, where he has worked on low-end processors and SoC for IoT and other applications.

Prof. Chester Park received his Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Korea, in 2006. After about two years with Samsung Electronics Inc., Giheung, Korea, he joined Ericsson Research, USA, where he developed various signal processing algorithms for wireless communications. Since 2013, he has been with Konkuk University, Seoul, Korea, working on hardware accelerator design for signal processing algorithms.

 

 
Accelerators and Enablement for Application-Specific Multicore Platforms

Title: “Accelerators and Enablement for Application-Specific Multicore Platforms”
Speaker: Dr. Andreas Herkersdorf, Electrical & Computer Engineering, Technische Universität München

Date and Time: Monday, July 31, 2017 at 2:00PM-3:00PM

Location: DBH 3011

Abstract: Multicore technology plays a pivotal role in conquering key societal challenges. For example, safe, ecological mobility, wide-spread rollout of eHealth, smart industrial automation and the development of a secure, high-bandwidth, low-latency mobile communication infrastructure for Industry 4.0, all these application domains are critically dependent on high-performance, low power and dependable computing. However, multicore technology also comes with a number of unique challenges for industry and academia. Today, the efficient utilization of massively parallel computing resources largely depends on the experience of individual programmers.

Application-specific accelerators and generic enablement building blocks for Multicore System on Chip (MCSoC) platforms are research foci at the Chair for Integrated Systems at TU München. These building blocks support a more performant, energy efficient, easier to use and more resilient deployment of multicore processors by application programmers and system integrators. In my talk, I will present current and past research projects on wire-speed traffic distribution among Software Defined Networking (SDN) nodes, interconnect virtualization for Network on Chip and processing node resilience, efficient multicore deployment in legacy automotive CAN networks and on-chip diagnosis for effective software debugging.

Biography: Andreas Herkersdorf is a professor at the Department of Electrical and Computer Engineering and also adjunct to the Department of Informatics at Technische Universität München (TUM). He received the diploma degree from TUM in 1987 and the Dr. degree from ETH Zurich, Switzerland, in 1991, both in electrical engineering. Between 1988 and 2003, he has been a research staff member and manager at the IBM Zurich Research Laboratory in Rüschlikon, Switzerland.

Since 2003, Dr. Herkersdorf is head of the Chair for Integrated Systems at TUM. He is a senior member of the IEEE, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer, Elsevier and deGruyter journals for design automation, communications electronics and information technology. His research interests include application-specific multi-processor architectures, IP network processing, Network on Chip, system level SoC modeling and design space exploration methods, and self-aware fault-tolerant computing.

 
“Optimizing Private Local Memories in Heterogeneous Architectures”

Title: “Optimizing Private Local Memories in Heterogeneous Architectures”

Speaker: Christian Pilato, Università della Svizzera italiana (USI), Lugano, Switzerland

Date and Time: Wednesday, June 14, 2017 at 11:00AM-12:00PM

Location: ICS 432

Abstract:

Modern Systems-on-Chip (SoC) architectures and state-of-the-art computing platforms that integrate CPUs with FPGAs are heterogeneous systems featuring an increasing number of hardware accelerators. Private local memories play a key role in the design of these components both with respect to performance optimization and because they are responsible for most of their area and power dissipation. Each local memory unit is usually implemented with a multibank microarchitecture based on the combined requirements of each hardware block accessing the corresponding data. However, the creation of these multibank memory microarchitectures is not well supported by current design flows, and the designers must perform this tedious and error-prone process manually.

In this talk, I will present a system-level methodology for the generation of multi-bank memories in heterogeneous architectures. The methodology is supported by Mnemosyne, an open-source prototype CAD tool that can be easily integrated into commercial design flows. Mnemosyneincludes various technology-aware optimizations to reduce the memory cost (area and power) by efficiently reusing the physical banks for storing different data. With Mnemosyne,we can reduce the memory cost of single accelerators by up to 45%. Moreover, when reusing memory IPs across accelerators, we achieve area savings that range between 17% and 55% compared to the case where the memory elements are designed separately.

Biography:

Christian Pilato is a Postdoctoral Researcher at the ALaRi institute of Università della Svizzera italiana (USI), Lugano, Switzerland. He received the Laurea degree in computer engineering and the Ph.D. degree in information technology from Politecnico di Milano, Italy, in 2007 and 2011, respectively. From 2013 to 2016, he was a Postdoctoral Research Scientist with the Department of Computer Science, Columbia University, USA. He has been visiting researcher at NanGate, Chalmers University of Technology, and Delft University of Technology. 
His current research interests include high-level synthesis, reconfigurable systems and system-on-chip architectures, with emphasis on memory aspects. He has actively participated in several projects sponsored by the European Union and DARPA, as well as a research center supported by SRC. Dr. Pilato served as the Program Chair of the Embedded and Ubiquitous Conference (EUC) in 2014. He is currently involved in the program committees of many conferences on embedded systems, CAD, and reconfigurable architectures, such as FPL, DATE, and CASES. He is a Member of IEEE and ACM.

 
Mobile and Emerging Computing Systems: challenges and research opportunities

Title: “Mobile and Emerging Computing Systems: challenges and research opportunities”

Speaker: Dr. Raid Ayoub, Intel Strategic CAD Lab, Portland, Oregon, USA

Date and Time: Friday, June 23, 2017 at 11:00AM-12:00PM

Location: DBH 3011

Abstract:

The computing systems have been evolving at a fast pace and they are increasingly ubiquitous. This trend is driven by advancements in mobile technologies and emerging of Internet-of-Things (IoT) as well as new applications. However, the complexity and diversity of these systems continue to rise, which require transformative design automation solutions to meet stringent design metrics, e.g. time-to-market. This talk will address research problems in mobile computing at the system level with some emphasis on energy efficiency and power budgeting of the CPU-GPU subsystem as well as user-experience related problems (e.g. skin temperature estimation and control). In addition, this talk will discuss emerging challenges and future research problems in the domain of IoT systems with a focus on End-to-End system design.

Biography:

Raid Ayoub received his Ph.D. degree in computer engineering from the department of computer science and engineering, University of California at San Diego in 2011.Currently he is a research scientist at the Strategic CAD Labs of Intel Corporation. He has published more than 30 journal and conference papers. His research interests include run-time optimizations, dynamic control, system modeling, human cyber-physical systems/IoT, dynamic power and thermal management, machine learning, and design automation.

 
Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics

Title:  “Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics”

Speaker: Prof. Axel Jantsch, TU Wien

Date and Time:  Friday,  June 16, 2017 at 11 A.M.

Location: 2430 Engineering Hall

Host: Prof. Nikil Dutt

Abstract: In healthcare, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. This walk presents a remote monitoring and diagnostic system that provides a holistic perspective of patients and their health conditions. It discusses how the concept of self-awareness can be used in various parts of the system such as information collection through wearable sensors, confidence assessment of the sensory data, the knowledge base of the patient’s health situation, and automation of reasoning about the health situation. This approach to self-awareness provides

(i) situation awareness to consider the impact of variations such as sleeping, walking, running, and resting,

(ii) system personalization by reflecting parameters such as age, body mass index, and gender, and

(iii) the attention property of self-awareness to improve the energy efficiency and dependability of the system via adjusting the priorities of the sensory data collection.

Biography:

 Axel Jantsch received the Dipl.Ing. and Dr. Tech. degrees from TU Wien, Vienna, Austria, in 1988 and 1992, respectively. He was with Siemens Austria, Vienna, Austria, as a system validation engineer from 1995 to 1997. From 1997 to 2002 he was an associate professor and from 2002 to 2014 he was full professor of Electronic Systems Design at the Royal Institute of Technology (KTH), Stockholm, Sweden. Since 2014 he has been professor of Systems on Chip at TU Wien. He has published about 300 papers in international conferences and journals and one book in the areas of Systems on chip, networks on chip and embedded systems. He has served on a large number of technical program committees of international conferences, such as FDL, DATE, CODES ISSS, SOC, NOCS, and others. He has been the TPC Chair of SSDL/ FDL 2000, the TPC Co-Chair of CODES ISSS 2004, the General Chair of CODES ISSS 2005, and the TPC Co-Chair of NOCS 2009. From 2002 to 2007, he was a subject area editor for the Journal of System Architecture. He is on the editorial board for IEEE Design and Test and for the Leibniz Transactions on Embedded Systems. He is a member of the IEEE. His main research interest is on networks on chip and self-awareness in systems on chip and embedded systems.

 
Heterogeneous Chip Architectures for Big Data Analytics

Title: “Heterogeneous Chip Architectures for Big Data Analytics”

Speaker: Houman Homayoun, George Mason University, Virginia

Date and Time: Friday, April 28, 2017 at 11:00AM

Location: 2430 Engineering Hall

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Low Energy, a New Trend for Lightweight Cryptography

Title: “Low Energy, a New Trend for Lightweight Cryptography”

Speaker: Dr. Francesco Regazzoni, ALaRI Institute of Università della Svizzera italiana, Lugano, Switzerland

Date and Time:  Wednesday, February 1, 2017 at 11:00 a.m.

Location: DBH 4011

Host: Prof. Nikil Dutt

Abstract: In the last decade, several lightweight block ciphers and hash functions have been proposed. One of the metrics, so far largely unexplored, which has to be used to identify a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers, this operation is the encryption of one plaintext.

This talk will address several approaches for reducing the energy consumption of existing block ciphers, touching the design space of the AES algorithm, to which few algorithmic optimizations are applied.

The gained experience lead to the design of Midori, the first block cipher designed to optimize the energy consumed per bit in encryption or decryption operation. Each component of the circuit, as well as its entire architecture of the cipher, have been optimized for energy, and design choices leading to low energy consumption in an electrical circuit were taken. Achieved results demonstrate that the energy consumption of Midori64 and Midori128 is much lower that current stateof the art.

Biography: Dr. Francesco Regazzoni is a senior researcher at the the ALaRI Institute of Universita’ della Svizzera italiana (Lugano, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of Universita’ della Svizzera italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft, and visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, EPFL, and NTU Singapore. His research interests are mainly focused on embedded systems security, covering in particular side channel attacks, electronic design automation for security, hardware Trojans, low energy cryptography, and post quantum security. He has published more than 70 journal and conference papers in the area of security and design automation, and has been in the technical program committed of top conferences of the area. Francesco is the principal investigator and project leader at Universita’ della Svizzera italiana of the projects (SAFECrypto, exploring lattice-based constructions as building blocks for quantum resistant cryptography), and CERBERO (design tools for Cyber-Physical Systems).

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High Level Synthesis – Some Challenging Problems

Title: “High Level Synthesis – Some Challenging Problems”

Speaker: George A. Constantinides, Imperial College London, UK

Date and Time: Wednesday, November 16, 2016 at 11:00 A.M.

Location: Engineering Hall 2430

Host: Professor Nikil Dutt

Abstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem, but one that appears to now have come to age. Both the demand for, and the supply of, quality HLS tools is now in place. However, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular, I will look at the problem of customization of memory for heap manipulating programs, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems.

Biography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA, FPT, and FPL conferences. He enjoys hard problems and espresso.

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Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow

Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow”

Speaker: Christian Krieg, Vienna University of Technology, Vienna, Austria

Date and Time: Thursday, November 17, 2016 at 2:00 PM

Location: Donald Bren Hall 3011

Host:  Professor Nikil Dutt

Abstract: We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events, such as rare values or sequences. While in most cases these trigger circuits are able to hide a Trojan attack, exhaustive functional simulation and testing will reveal the Trojan due to violation of the specification. Our trigger behaves functionally and formally equivalent to the hardware description language (HDL) specification throughout the entire FPGA design flow, until the design is written by the place-and-route tool as bitstream configuration file. From then, Trojan payload is always on. We implement the trigger signal using a 4-input lookup table (LUT), each of the inputs connecting to the same signal. This lets us directly address the least significant bit (LSB) and most significant bit (MSB) of the LUT. With the remaining 14 bits, we realize a “magic” unary operation. This way, we are able to implement 16 different Triggers. We demonstrate the attack with a simple example and discuss the effectiveness of the recent detection techniques unused circuit identification (UCI), functional analysis for nearly-unused circuit identification (FANCI) and VeriTrust in order to reveal our trigger.

Biography: Christian Krieg received the bachelor’s and master’s degree in electrical engineering from TU Wien and is now pursuing his PhD studies on hardware security at TU Wien. His research focuses on design-level hardware Trojan design and detection. He also works on reasonable threat models for hardware Trojan attacks. Christian recently received the William McCalla best paper award for a novel hardware Trojan implementation. At a wider scope, Christian’s research interests include cyber-physical systems security and IoT security.

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Adaptive Design: Tackling Variability Challenges in VLSI Circuits

Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”

Speaker: Professor Mingoo Seok, Columbia University, New York

Date:  Friday, April 22, 2016

Time:  3:00PM

Location:  Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host: Prof. Payam Heydari

Abstract: In this talk, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage, chip temperature, manufacturing process, and transistor aging have imposed a large amount of pessimistic margins in clock frequency, voltage, and device size, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead, in-situ, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented.

Bio:

Mingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University, South Korea, in 2005, and the MS and PhD degree from University of Michigan in 2007 and 2011, respectively, all in electrical engineering. He was a member of technical staff in Texas Instruments, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems, including ultra-low-power computing systems, computing systems for machine learning, adaptive circuits and architecture, and non-conventional computing systems.

He received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies, 2005 Doctoral Fellowship from the same organization, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013, and IEEE Transactions on VLSI Systems since 2015.