Seminars at CECS

Accelerators and Enablement for Application-Specific Multicore Platforms

Title: “Accelerators and Enablement for Application-Specific Multicore Platforms”
Speaker: Dr. Andreas Herkersdorf, Electrical & Computer Engineering, Technische Universität München

Date and Time: Monday, July 31, 2017 at 2:00PM-3:00PM

Location: DBH 3011

Abstract: Multicore technology plays a pivotal role in conquering key societal challenges. For example, safe, ecological mobility, wide-spread rollout of eHealth, smart industrial automation and the development of a secure, high-bandwidth, low-latency mobile communication infrastructure for Industry 4.0, all these application domains are critically dependent on high-performance, low power and dependable computing. However, multicore technology also comes with a number of unique challenges for industry and academia. Today, the efficient utilization of massively parallel computing resources largely depends on the experience of individual programmers.

Application-specific accelerators and generic enablement building blocks for Multicore System on Chip (MCSoC) platforms are research foci at the Chair for Integrated Systems at TU München. These building blocks support a more performant, energy efficient, easier to use and more resilient deployment of multicore processors by application programmers and system integrators. In my talk, I will present current and past research projects on wire-speed traffic distribution among Software Defined Networking (SDN) nodes, interconnect virtualization for Network on Chip and processing node resilience, efficient multicore deployment in legacy automotive CAN networks and on-chip diagnosis for effective software debugging.

Biography: Andreas Herkersdorf is a professor at the Department of Electrical and Computer Engineering and also adjunct to the Department of Informatics at Technische Universität München (TUM). He received the diploma degree from TUM in 1987 and the Dr. degree from ETH Zurich, Switzerland, in 1991, both in electrical engineering. Between 1988 and 2003, he has been a research staff member and manager at the IBM Zurich Research Laboratory in Rüschlikon, Switzerland.

Since 2003, Dr. Herkersdorf is head of the Chair for Integrated Systems at TUM. He is a senior member of the IEEE, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer, Elsevier and deGruyter journals for design automation, communications electronics and information technology. His research interests include application-specific multi-processor architectures, IP network processing, Network on Chip, system level SoC modeling and design space exploration methods, and self-aware fault-tolerant computing.

 
Mobile and Emerging Computing Systems: challenges and research opportunities

Title: “Mobile and Emerging Computing Systems: challenges and research opportunities”

Speaker: Dr. Raid Ayoub, Intel Strategic CAD Lab, Portland, Oregon, USA

Date and Time: Friday, June 23, 2017 at 11:00AM-12:00PM

Location: DBH 3011

Abstract:

The computing systems have been evolving at a fast pace and they are increasingly ubiquitous. This trend is driven by advancements in mobile technologies and emerging of Internet-of-Things (IoT) as well as new applications. However, the complexity and diversity of these systems continue to rise, which require transformative design automation solutions to meet stringent design metrics, e.g. time-to-market. This talk will address research problems in mobile computing at the system level with some emphasis on energy efficiency and power budgeting of the CPU-GPU subsystem as well as user-experience related problems (e.g. skin temperature estimation and control). In addition, this talk will discuss emerging challenges and future research problems in the domain of IoT systems with a focus on End-to-End system design.

Biography:

Raid Ayoub received his Ph.D. degree in computer engineering from the department of computer science and engineering, University of California at San Diego in 2011.Currently he is a research scientist at the Strategic CAD Labs of Intel Corporation. He has published more than 30 journal and conference papers. His research interests include run-time optimizations, dynamic control, system modeling, human cyber-physical systems/IoT, dynamic power and thermal management, machine learning, and design automation.

 
Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics

Title:  “Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics”

Speaker: Prof. Axel Jantsch, TU Wien

Date and Time:  Friday,  June 16, 2017 at 11 A.M.

Location: 2430 Engineering Hall

Host: Prof. Nikil Dutt

Abstract: In healthcare, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. This walk presents a remote monitoring and diagnostic system that provides a holistic perspective of patients and their health conditions. It discusses how the concept of self-awareness can be used in various parts of the system such as information collection through wearable sensors, confidence assessment of the sensory data, the knowledge base of the patient’s health situation, and automation of reasoning about the health situation. This approach to self-awareness provides

(i) situation awareness to consider the impact of variations such as sleeping, walking, running, and resting,

(ii) system personalization by reflecting parameters such as age, body mass index, and gender, and

(iii) the attention property of self-awareness to improve the energy efficiency and dependability of the system via adjusting the priorities of the sensory data collection.

Biography:

 Axel Jantsch received the Dipl.Ing. and Dr. Tech. degrees from TU Wien, Vienna, Austria, in 1988 and 1992, respectively. He was with Siemens Austria, Vienna, Austria, as a system validation engineer from 1995 to 1997. From 1997 to 2002 he was an associate professor and from 2002 to 2014 he was full professor of Electronic Systems Design at the Royal Institute of Technology (KTH), Stockholm, Sweden. Since 2014 he has been professor of Systems on Chip at TU Wien. He has published about 300 papers in international conferences and journals and one book in the areas of Systems on chip, networks on chip and embedded systems. He has served on a large number of technical program committees of international conferences, such as FDL, DATE, CODES ISSS, SOC, NOCS, and others. He has been the TPC Chair of SSDL/ FDL 2000, the TPC Co-Chair of CODES ISSS 2004, the General Chair of CODES ISSS 2005, and the TPC Co-Chair of NOCS 2009. From 2002 to 2007, he was a subject area editor for the Journal of System Architecture. He is on the editorial board for IEEE Design and Test and for the Leibniz Transactions on Embedded Systems. He is a member of the IEEE. His main research interest is on networks on chip and self-awareness in systems on chip and embedded systems.

 
Heterogeneous Chip Architectures for Big Data Analytics

Title: “Heterogeneous Chip Architectures for Big Data Analytics”

Speaker: Houman Homayoun, George Mason University, Virginia

Date and Time: Friday, April 28, 2017 at 11:00AM

Location: 2430 Engineering Hall

(more…)

 
Low Energy, a New Trend for Lightweight Cryptography

Title: “Low Energy, a New Trend for Lightweight Cryptography”

Speaker: Dr. Francesco Regazzoni, ALaRI Institute of Università della Svizzera italiana, Lugano, Switzerland

Date and Time:  Wednesday, February 1, 2017 at 11:00 a.m.

Location: DBH 4011

Host: Prof. Nikil Dutt

Abstract: In the last decade, several lightweight block ciphers and hash functions have been proposed. One of the metrics, so far largely unexplored, which has to be used to identify a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers, this operation is the encryption of one plaintext.

This talk will address several approaches for reducing the energy consumption of existing block ciphers, touching the design space of the AES algorithm, to which few algorithmic optimizations are applied.

The gained experience lead to the design of Midori, the first block cipher designed to optimize the energy consumed per bit in encryption or decryption operation. Each component of the circuit, as well as its entire architecture of the cipher, have been optimized for energy, and design choices leading to low energy consumption in an electrical circuit were taken. Achieved results demonstrate that the energy consumption of Midori64 and Midori128 is much lower that current stateof the art.

Biography: Dr. Francesco Regazzoni is a senior researcher at the the ALaRI Institute of Universita’ della Svizzera italiana (Lugano, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of Universita’ della Svizzera italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft, and visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, EPFL, and NTU Singapore. His research interests are mainly focused on embedded systems security, covering in particular side channel attacks, electronic design automation for security, hardware Trojans, low energy cryptography, and post quantum security. He has published more than 70 journal and conference papers in the area of security and design automation, and has been in the technical program committed of top conferences of the area. Francesco is the principal investigator and project leader at Universita’ della Svizzera italiana of the projects (SAFECrypto, exploring lattice-based constructions as building blocks for quantum resistant cryptography), and CERBERO (design tools for Cyber-Physical Systems).

View Details Here

 
High Level Synthesis – Some Challenging Problems

Title: “High Level Synthesis – Some Challenging Problems”

Speaker: George A. Constantinides, Imperial College London, UK

Date and Time: Wednesday, November 16, 2016 at 11:00 A.M.

Location: Engineering Hall 2430

Host: Professor Nikil Dutt

Abstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem, but one that appears to now have come to age. Both the demand for, and the supply of, quality HLS tools is now in place. However, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular, I will look at the problem of customization of memory for heap manipulating programs, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems.

Biography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA, FPT, and FPL conferences. He enjoys hard problems and espresso.

View more here

 
Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow

Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow”

Speaker: Christian Krieg, Vienna University of Technology, Vienna, Austria

Date and Time: Thursday, November 17, 2016 at 2:00 PM

Location: Donald Bren Hall 3011

Host:  Professor Nikil Dutt

Abstract: We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events, such as rare values or sequences. While in most cases these trigger circuits are able to hide a Trojan attack, exhaustive functional simulation and testing will reveal the Trojan due to violation of the specification. Our trigger behaves functionally and formally equivalent to the hardware description language (HDL) specification throughout the entire FPGA design flow, until the design is written by the place-and-route tool as bitstream configuration file. From then, Trojan payload is always on. We implement the trigger signal using a 4-input lookup table (LUT), each of the inputs connecting to the same signal. This lets us directly address the least significant bit (LSB) and most significant bit (MSB) of the LUT. With the remaining 14 bits, we realize a “magic” unary operation. This way, we are able to implement 16 different Triggers. We demonstrate the attack with a simple example and discuss the effectiveness of the recent detection techniques unused circuit identification (UCI), functional analysis for nearly-unused circuit identification (FANCI) and VeriTrust in order to reveal our trigger.

Biography: Christian Krieg received the bachelor’s and master’s degree in electrical engineering from TU Wien and is now pursuing his PhD studies on hardware security at TU Wien. His research focuses on design-level hardware Trojan design and detection. He also works on reasonable threat models for hardware Trojan attacks. Christian recently received the William McCalla best paper award for a novel hardware Trojan implementation. At a wider scope, Christian’s research interests include cyber-physical systems security and IoT security.

View Details

 
Adaptive Design: Tackling Variability Challenges in VLSI Circuits

Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”

Speaker: Professor Mingoo Seok, Columbia University, New York

Date:  Friday, April 22, 2016

Time:  3:00PM

Location:  Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host: Prof. Payam Heydari

Abstract: In this talk, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage, chip temperature, manufacturing process, and transistor aging have imposed a large amount of pessimistic margins in clock frequency, voltage, and device size, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead, in-situ, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented.

Bio:

Mingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University, South Korea, in 2005, and the MS and PhD degree from University of Michigan in 2007 and 2011, respectively, all in electrical engineering. He was a member of technical staff in Texas Instruments, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems, including ultra-low-power computing systems, computing systems for machine learning, adaptive circuits and architecture, and non-conventional computing systems.

He received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies, 2005 Doctoral Fellowship from the same organization, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013, and IEEE Transactions on VLSI Systems since 2015.

 
Hardware Security in the Zynq All-Programmable Soc

Title: “Hardware Security in the Zynq All-Programmable Soc”

Speaker: Dr. Steve Trimberger, Xilinx

Date:  Friday, October 2, 2015

Time:  2:00 p.m.

Location:  Donald Bren Hall 4011

Host: Prof. Fadi J. Kurdahi

Abstract: FPGAs have grown from a simple logic replacement to fully-programmable SoC, with multi-core CPU subsystems, a broad spectrum of peripherals, hundreds of thousands of gates of programmable logic and high-speed multi-gigabit transceivers. As the complexity of the underlying hardware has grown, so has the value of the applications built in them and the data handled by them. Traditional FPGA bitstream security has been enhanced to address these greater security requirements. This talk presents an overview of hardware security issues and the security features of the Zynq All- Programmable SoC. The secure boot process includes asymmetric and symmetric authentication as well as symmetric encryption to protect software and programmable hardware during programming.During operation the hardware can disable test ports, monitor on-chip power and temperature and detect tampering with configuration data. ARM Trust Zone is integrated through the AXI busses into both the processor and the programmable logic subsystems.

Bio: Dr. Stephen Trimberger holds a M.S. degree in ICS from UCI and a Ph.D. degree from California Institute of Technology. Since 1988, he has been employed at Xilinx, where he is currently Xilinx Fellow heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose, California. He was the technical leader for the XC4000 design automation software, developed a dynamically -reconfigurable multi-context FPGA, led the architecture definition group for the Xilinx XC4000X device families and designed the Xilinx bitstream security functions in the Virtex families of FPGAs. He led the group that developed the first die- stacked 3D FPGA prototype at Xilinx. He has served as Design Methods Chair for the Design Automation Conference, Program Chair and General Chair for the ACM/SIGDA FPGA Symposium and on the technical programs of numerous Workshops and Symposia. He has authored five books and dozens of papers on design automation, FPGA architectures and hardware security. He has more than 220 patents in IC design, FPGA and ASIC architecture, CAE, hardware security and cryptography. His innovations appear today in nearly all commercial FPGA devices. He is a Fellow of the ACM and a Fellow of the IEEE.

View Details Here

 

 
Resilience is a Critical Issue for Large-scale Platform

Speaker:  Prof. Yves Robert, Ecole Normale Supérieure de Lyon, France

Title:  Resilience is a Critical Issue for Large-scale Platform

Date:  Monday, May 18, 2015

Time:  11:00 a.m. – 12:00 p.m.

Location:  Harut Barsamian Colloquia Room (Engineering Hall 2430)

Host:  Prof. Jean-Luc Gaudiot

Abstract: Resilience is a critical issue for large-scale platforms. This talk will survey fault-tolerant techniques for high-performance computing:
– Overview of failure types and typical probability distributions
– Brief discussion of application-specific techniques, such as ABFT
– The standard general-purpose technique, checkpoint and     rollback recovery
– Recent extensions with replication, prediction and silent error detection
– Relevant execution scenarios, evaluated and compared through quantitative models.
The talk includes several illustrative examples and targets a general audience.

Bio: Yves Robert received his PhD degree from Institut National Polytechnique de Grenoble. He is currently a full professor in the Computer Science Laboratory LIP at ENS Lyon. He is the author of 7 books, 130+ papers published in international journals, and 200+ papers published in international conferences.  He is the editor of 11 book proceedings and 13 journal special issues.  He is the advisor of 28 PhD theses.  His main research interests are scheduling techniques and resilient algorithms for large-scale platforms. Yves Robert served on many editorial boards, including IEEE TPDS.  He was the program chair of HiPC’2006 in Bangalore, IPDPS’2008 in Miami, ISPDC’2009 in Lisbon, ICPP’2013 in Lyon and HiPC’2013 in Bangalore. He is a Fellow of the IEEE. He has been elected a Senior Member of Institut Universitaire de France in 2007 and renewed in 2012.  He has been awarded the 2014 IEEE TCSC Award for Excellence in Scalable Computing.  He holds a Visiting Scientist position at the University of Tennessee, Knoxville since 2011.

 

 

 
CMOS Process Variations: A “Critical Operation Point” Hypothesis

Title: CMOS Process Variations: A “Critical Operation Point” Hypothesis

Speaker: Dr. Janak H. Patel

Date: May 2, 2012

Time: 3:30-4:30 P.M.

Location: DBH 3011

Host: Professor Nikil Dutt

 

 
A Client-centric Approach to Interoperable Clouds

Speaker: Mukesh Singhal, Department of Computer Science, University of California, Merced

Title: A Client-centric Approach to Interoperable Clouds

Date: Friday, December 6, 2013

Time: 11:00am – 12:00pm

Location: Donald Bren Hall 6011

Abstract: Cloud computing offers several benefits in terms of scalability, cost and performance. These benefits have contributed to the wide-scale acceptance of the cloud computing paradigm and growing adoption by the industry. With this growth, limitations of this paradigm are beginning to surface. One such limitation is that contemporary clouds are not interoperable. This limitation arises due to proprietary technologies, heterogeneous interfaces and the tight tethering of service offerings to the host cloud. Current research solutions for enabling cloud interoperability are predominantly provider-centric, requiring cloud providers to adopt and implement the changes that facilitate interoperation. This approach faces several hurdles and can take a long time to hit the market. In the meantime, a client-centric approach to interoperation is necessary for providing its benefits to consumers in the current cloud ecosystem. To this end, a novel framework for cloud interoperation called collaborative cloud computing is proposed. The proposed framework provides dynamic, on-the-fly collaborations and resource sharing among cloud-based services, without pre-established collaboration agreements or standardized interfaces, through use of client-controlled mediating agents called proxies.

Bio: Mukesh Singhal is a Chancellor’s Professor in the Computer Science and Engineering program at the University of California, Merced. He received a PhD degree in Computer Science from the University of Maryland, College Park, in May 1986. From 1986 to 2001, he was a faculty in the department of Computer and Information Science at The Ohio State University. From 1998 to 2001, he served as the program director of the Operating Systems and Compilers program at the National Science Foundation. From 2001 to 2012, he was a Professor and Gartner Group endowed chair in Network Engineering in the Department of Computer Science at The University of Kentucky. His current research interests include distributed and cloud computing, cyber-security, and computer networks. He has published over 240 refereed articles in these areas. He is a Fellow of IEEE and he was a recipient of 2003 IEEE Technical Achievement Award. He has coauthored four books titled “Advanced Concepts in Operating Systems”, McGraw-Hill, New York, 1994, “Distributed Computing Systems”, Cambridge University Press 2007, “Data and Computer Communications: Networking and Internetworking”, CRC Press, 2001, and “Readings in Distributed Computing Systems”, IEEE Computer Society Press, 1993. He has served in the editorial board of “IEEE Trans. on Dependable and Secure Computing”, “IEEE Trans. on Parallel and Distributed Systems”, “IEEE Trans. on Data and Knowledge Engineering”, and “”IEEE Trans. on Computers”.

 

 
The Confluence of Communications, Sensing and Control in Large Scale Wireless Networks

Speaker:  Prof. Urbashi Mitra, Electrical Engineering, University of Southern California

Title:  The Confluence of Communications, Sensing and Control in Large Scale Wireless Networks

Date:  Friday, November 8, 2013

Time:  11:00am – 12:00pm

Location:  Donald Bren Hall 6011

Abstract: Modern wireless technology enables the vision of future large scale systems such as the SmartGrid, a network of ubiquitous and heterogeneous devices wirelessly connected to the Internet, and wireless health monitoring and health modifying sensor networks over communities and not just individuals.  All of these applications necessitate methods that simultaneously consider scale, communication, sensing and control. In this talk, key elements of realizing this vision are examined.  We shall focus on novel active control methods for networks described by partially observable Markov decision processes.  Such models are very general and can encompass sensing networks, as well as communication networks.  Following an innovations approach, a Kalman-like filter is derived to estimate the underlying system state.  As a case-study, numerical results are provided for physical activity detection in a heterogeneous wireless body area network.  We further examine distributed estimation in large scale networks with time-correlated behavior and explore how modern statistical methods such as compressed sensing can be applied to both the distributed estimation problem as well as the network control problem.

Bio: Urbashi Mitra received the B.S. and the M.S. degrees from the University of California at Berkeley and her Ph.D. from Princeton University.   She is currently a Professor in the Ming Hsieh Department of Electrical Engineering at the University of Southern California.  She is a member of the IEEE Information Theory Society’s Board of Governors (2002-2007, 2012-2014) and the IEEE Signal Processing Society’s Technical Committee on Signal Processing for Communications and Networks (2012-2014). She is the recipient of:  2012 Globecom Signal Processing for Communications Symposium Best Paper Award, 2012 NAE Lillian Gilbreth Lectureship, USC Center for Excellence in Research Fellowship (2010-2013), the 2009 DCOSS Applications & Systems Best Paper Award, IEEE Fellow (2007), Texas Instruments Visiting Professor (Fall 2002, Rice University), 2001 Okawa Foundation Award, 2000 OSU College of Engineering Lumley Award for Research, and a 1996 NSF CAREER Award.  Dr. Mitra has been/is an Associate Editor for the following IEEE publications: Transactions on Signal Processing (2012–), Transactions on Information Theory (2007-2011), Journal of Oceanic Engineering (2006-2011), and Transactions on Communications (1996-2001).  Dr. Mitra has held visiting appointments at: the Delft University of Technology, Stanford University, Rice University, and the Eurecom Institute. She served as co-Director of the Communication Sciences Institute at the University of Southern California from 2004-2007.  Her research interests are in: wireless communications, communication and sensor networks, detection and estimation and the interface of communication, sensing and control.

 
Building Fake Body Parts: Real-Time Digital Mockups of Physiological Systems

Title:  Building Fake Body Parts: Real-Time Digital Mockups of Physiological Systems
Speaker: Prof. Frank Vahid, University of California, Riverside
Location: 6011 Donald Bren Hall
Date/Time: Friday, October 26, 2012, 11:00am – 12:00pm
Host: Prof. Eli Bozorgzadeh

Abstract: Designing computer-based medical devices like pacemakers or ventilators is hard, in part because testing can’t be done on real humans. PC-based simulations are slow and inaccurate. Using physical mockups, like connecting a ventilator device to a balloon acting as a lung, can’t support sufficiently diverse scenarios, like fluid in the lungs. This talk describes joint UCR/UCI work on developing “digital mockups” — models of physiological systems that execute in real-time, supporting thorough testing of device software. We show that FPGAs (field-programmable gate arrays) — widely-available programmable chips having a unique execution approach that we’ll describe — are an excellent match for executing physiological models, yielding order-of-magnitude speedups over PCs, GPUs, and other computing approaches. The talk describes the synthesis approach to automatically converting models, consisting of thousands of differential equations, into networks of processing elements on FPGAs. Real-time execution of physiological models can also be useful in building complete human simulators, used today medical and nursing schools. More broadly, real-time execution of physical systems (chemical, biological, mechanical, physiological, etc.) can be useful in the design of a wide variety of what today are called cyber-physical systems– systems where computers interact closely with the physical world – including automobiles, aircraft, medical equipment, military equipment, manufacturing systems, and much more.

Bio: Frank Vahid is a Professor of Computer Science and Engineering at the University of California, Riverside (B.S. 1988 Univ. of Illinois in 1988, M.S./Ph.D. 1990/1994 Univ.of California, Irvine. He is author of several textbooks on embedded systems and digital design. His current research interests include creating technologies for cyber-physical systems (http://www.cs.ucr.edu/~vahid/digitalmockups/), developing customizable assistive monitoring systems for home-alone aging/disabled persons and their caretakers http://www.cs.ucr.edu/~vahid/assistivemonitoring/, and creating the next generation of online interactive animated learning material (http://pcpp.zyante.com).
View Details Here

 
Addressing Supply Chain Security with Split Manufacturing

Speaker: Dr. Ted Huffmire, Naval Postgraduate School, Monterey, CA
Title: Addressing Supply Chain Security with Split Manufacturing
Date: July 27, 2012
Time:11:00am
Location: Donald Bren Hall 3011
CECS Host: Prof. Nikil Dutt

Abstract: Security is an essential design goal in computer architecture, and security is a concern throughout the entire lifecycle of a system. The process of designing hardware requires trusting intellectual property (IP) cores and computer-aided design (CAD) tools developed by third parties, as well as the fabrication, packaging, assembly, and delivery of the final system. Valuable IP is vulnerable to theft and modification during tape-out, even if a perfect design free of security flaws is sent to the foundry. Of course, no design is ever perfect, and having a trusted foundry does not solve the problem of flawed designs. Furthermore, the trusted foundry may not have the capability to deliver the most aggressive technology node, volume, yield, or cost. Even the extraordinary step of building everything from scratch in-house, including all of the tool chains, both digital and analog, is not guaranteed to result in a trustworthy design.

Bio: Ted Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey, California. His research spans both computer security and computer architecture, focusing on hardware-oriented security and the development of policy enforcement mechanisms for application-specific devices. He has a Ph.D. in computer science from the University of California, Santa Barbara. He is a member of the IEEE and the ACM. The views presented in this talk are those of the speaker and do not necessarily reflect the views of the United States Department of Defense.

View Details Here