Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications

by Ilya Michailovich Issenin

With increasing processing power demands of embedded applications and technology advances, Multiprocessor Systems-on-Chip (MPSoCs) become prevalent in embedded systems. The memory subsystem is a large and critical contributor to both energy and performance of such systems, requiring system designers to perform exploration of low power memory organizations. In this dissertation we present an automated approach for data memory subsystem customization for streaming applications. Our approach allows modification of the program to use custom scratch pad memory configurations comprising a hierarchical set of buffers for local storage of frequently reused data. Our data reuse analysis technique provides the system designer with a wide range of customized memory hierarchy organizations with different size and energy profiles and enables the system designer to explore feasible memory subsystem solutions that satisfy power and area constraints while still meeting task deadlines, both for uniprocessor and multiprocessor systems.

In modern multiprocessor embedded systems the communication subsystem also plays an important role in determining overall system power consumption and performance. We propose novel approaches that enables energy-aware co-synthesis of both memory and communication architectures for streaming applications targeting hierarchical bus-based and Network-on-Chip communication architectures. Our techniques achieve significant reduction in memory and communication subsystems energy consumption for data dominant applications, and allow system designers to explore custom scratch pad memory configuration for a range of power and area constraints.

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