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Kilo-Instruction Processors: Overcoming the Memory Wall

February 16, 2006 @ 3:00 pm - 4:00 pm PST

Kilo-Instruction Processors: Overcoming the Memory Wall

Speaker Professor Mateo Valero
Computer Architecture Dep. of the Polytechnical University of Catalunia
Catalunia, Spain
Location Computer Science 432
Date & Time February 16, 2006
Refreshments at 10:30am, followed by Lecture
Abstract Today’s systems have a very large and growing gap between processor and (DRAM) memory speeds, which results in very long memory latency and loss of performance. Many different techniques have been proposed to address this problem: cache memories, prefetching and other latency hiding techniques, and multithreading, to name a few. We proposed a different approach to solving this problem: a new type of out-of-order superscalar processor called the Kilo-Instruction Processor. Our design can have thousands of in-flight instructions using a scalable multi-check pointing mechanism. This allows memory access to be overlapped with the execution of a large number of other instructions and significantly improves performance. Kilo-Instruction Processors also offer advantages in multiprocessor systems, where the average memory latency is even longer. They enable implementation of other very desirable features via their check-pointing mechanism. For example, we can implement a multiprocessor transactional memory in hardware using checkpoints, which enables an effective implementation of sequential consistency. This talk will describe the main ideas of our work on Kilo-instruction processors, efficient
implementation options for this type of processors, and their use in the design of multiprocessor systems.
Biography  

Mateo Valero obtained his PhD at UPC in 1980. He is a Professor in the Computer Architecture Department of the Polytechnical University of Catalunia (UPC) in Spain and the director of the Barcelona Supercomputing Center, the National Supercomputing Center of Spain. His research interests are in the area of high performance computer architecture. He has published over 400 papers in this field. Dr. Valero is a Fellow of the IEEE, an Intel Distinguished Research Fellow and a Fellow of the ACM. He is a Correspondent Academic Member of the Spanish Royal Academy of Sciences. He is a winner of the “King Jaime I” award by the Generalitat Valenciana and the Spanish national award “Julio Rey Pastor” for his research in IT technologies. He is very proud that his home town of Alfamen named its Public College after him.

Details

Date:
February 16, 2006
Time:
3:00 pm - 4:00 pm PST
Event Category: