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Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design

Name: Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design
Start: 2008-03-03T15:00:00-08:00
End: 2008-03-03T16:00:00-08:00

March 3, 2008 @ 3:00 pm - 4:00 pm PST

by Gunar Schirner, University of California, Irvine
March 3, 2008
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Date:: March 3, 2008
Time:: 3:00 pm - 4:00 pm PST
Event Category:: PhD Defenses

Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design

March 3, 2008 @ 3:00 pm - 4:00 pm PST

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