Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems

by Amin Khajeh Djahromi

Location: Engineering Hall 2111

Date and Time: November 29, 2010 4:00pm

Prof. Pai H. Chou (Chair)
Prof. Stephen Jenks
Prof. Rainer Doemer

Designers of next generation Systems-on-Chip (SoCs) face daunting challenges in generating high yielding architectures that integrate vast amounts of logic and memories in a minimum die size, while simultaneously minimizing power consumption. Traditional design approaches attempt to guarantee 100% error-free SoCs. However, advanced manufacturing technologies will make it economically impractical to insist on a 100% error-free SoC in terms of area and power. Fortunately, many important application domains (e.g., communication and multimedia) are inherently error-aware, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. In such systems, the share of the SoC that is dedicated to embedded memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoC for most recent advanced wireless standards. Furthermore, a large portion of the memory is typically used for buffering data that already has a high level of redundancy.

Finally, from a network perspective, buffering memories are transparent across a hierarchy since they do not change the nature of the data stored, which allows for simple and efficient cross- layer techniques. In my thesis I investigated the effect of voltage over scaling on the embedded memories functionality. Then I proposed fault tolerant adaptive voltage scaling and adaptive body biasing as a mean of reducing power consumption in embedded memories. These techniques tradeoff reliability versus power savings as a function of the time varying quality of the incoming data, as long as the signal to noise ratio at the decision device is maintained at a desirable level. Moreover, I addressed the notion of error-awareness across different abstraction layers physical, application, network, and technology for the next generation SoCs. I showed that utilizing proposed techniques on embedded memories (mainly through aggressive ! voltage scaling) will result in a) appreciable power reduction in wire less systems depending on the application, b) savings in cost and area by reducing or eliminating the need for circuit redundancy, and c) achieving a higher “effective yield” by tolerating errors at the system level while keeping other parameters constant.