Due to the continuously increasing size and complexity of LSIs, the traditional Register-Transfer Level (RTL) design with Hardware Design Languages (HDLs) is approaching its limit on design productivity. High-level synthesis, which automatically synthesizes an RTL circuit from a behavioral description, is expected as a promising solution to improve design productivity. However, the LSI design has not been completely shifted from the traditional RTL design with HDLs to high-level synthesis yet since the quality of automatically synthesized RTL circuits through high-level synthesis can be inferior to that of human-designed ones, which is especially serious for large designs.

The goal of my work is to develop practical technologies of "high-level synthesis from large behavioral descriptions". In this talk, first, one of my thesis works, which revealed some problems in current technologies of high-level synthesis, is briefly presented. Then, previous/ongoing works which tackle with the problems are presented.