Pictures from Industrial Speaker Series Embedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond click on the thumbnails to view the full-sized images     The lecture was held at the McDonnell Douglas Auditorium view larger image             Jon Haigh and Mike Wilkerson are members of the team designing the Intel XScale embedded processor. view larger image             Jon and Mike chatting with CECS students before delivering their talk. Professor Alex Veidenbaum, left background, hosted the event. view larger image             Mike Wilkerson discussing embedded processor design challenges. At 90 nm, it is important to employ architectural techniques that emphasize power reduction. view larger image             Jon Haigh explaining cache memory design strategies for the XScale processor. view larger image             A lively Q & A session followed the presentation. view larger image
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